Stacked chip layout

Patent metadata

Field	Value
Publication number	US-2020151381-A1
Application number	US-202016746779-A
Country	US
Kind code	A1
Filing date	Jan 17, 2020
Priority date	Aug 30, 2013
Publication date	May 14, 2020
Grant date	—

Abstract

A stacked chip layout includes a central processing chip, a first active circuit block over the central processing chip, and a second active circuit block overlapping the first active circuit. The first and second active circuit blocks are within a perimeter of the central processing chip in a plan view. The stacked chip layout includes a first routing region on a same plane as the first active circuit block, and a second routing region on a same plane as the second active circuit block. The first routing region is between the second active circuit block and the central processing chip. The stacked chip layout includes a heat dissipation element over the second active circuit block and the second routing region. The second routing region is configured to convey heat from the first active circuit block to the heat dissipation element.

First claim

What is claimed is:

1 . A stacked chip layout comprising:
a central processing chip; a first active circuit block over the central processing chip; a second active circuit block over the first active circuit, wherein the second active circuit block overlaps the first active circuit block, and both the first active circuit block and the second active circuit block are within a perimeter of the central processing chip in a plan view; a first routing region on a same plane as the first active circuit block, wherein the first routing region is between the second active circuit block and the central processing chip; a second routing region on a same plane as the second active circuit block; and a heat dissipation element over the second active circuit block and the second routing region, wherein the second routing region is configured to convey heat generated by the first active circuit block to the heat dissipation element.

2 . The stacked chip layout of claim 1 , further comprising a local electrical connection, wherein the local electrical connection electrically connects the first active circuit block and the second active circuit block.

3 . The stacked chip layout of claim 2 , wherein the local electrical connection extends through the first routing region.

4 . The stacked chip layout of claim 2 , wherein the local electrical connection extends through the second routing region.

5 . The stacked chip layout of claim 1 , further comprising a substrate, wherein the central processing chip is on the substrate.

6 . The stacked chip layout of claim 5 , wherein the first routing region is configured to convey heat generated by the second active circuit block to the substrate.

7 . The stacked chip layout of claim 5 , further comprising a third routing region between the first active circuit block and the substrate, wherein the third routing region is configured to convey heat generated by the first circuit block to the substrate.

8 . The stacked chip layout of claim 7 , further comprising an electrical connection in the third routing region, wherein the electrical connection is electrically connected to the first active circuit block.

9 . The stacked chip layout of claim 1 , further comprising a dielectric layer between the first active circuit block and the second routing region.

10 . The stacked chip layout of claim 1 , further comprising a dielectric layer between the first active circuit block and the second active circuit block, wherein a material of the dielectric layer is different from a material of the first routing region.

11 . A stacked chip layout comprising:
a plurality of circuit block layers over a central processing chip, wherein each of the plurality of circuit block layers comprises:
an active circuit block, wherein the active circuit block of each of the plurality of circuit block layers includes a first portion overlapping the active circuit block of every other circuit block layer of the plurality of circuit block layers, and
a dielectric material on a same level as the active circuit block; and
a global conductive element electrically connecting the central processing chip to the active circuit block of each of the plurality of circuit block layers, wherein the global conductive element is routed through the first portion of the active circuit block of each of the plurality of circuit block layers.

12 . The stacked chip layout of claim 11 , wherein the global conductive element is spaced from the dielectric material of each of the plurality of circuit block layers.

13 . The stacked chip layout of claim 11 , further comprising an inter-level via layer (ILV), wherein the global conductive element extends through the ILV.

14 . The stacked chip layout of claim 13 , wherein the ILV is between the central processing chip and the plurality of circuit block layers.

15 . The stacked chip layout of claim 13 , wherein the ILV is between adjacent circuit block layers of the plurality of circuit block layers.

16 . The stacked chip layout of claim 13 , wherein the ILV comprises a dielectric, and a material of the ILV is different from a material of the dielectric material of at least one circuit block layer of the plurality of circuit block layers.

17 . The stacked chip layout of claim 11 , wherein each of the plurality of circuit block layers further comprises a local conductive element electrically connected to a corresponding active circuit block of the plurality of circuit block layers, and the local conductive element extends through the dielectric material of a corresponding of the plurality of circuit block layers.

18 . A stacked chip layout comprising:
a first active circuit block over a central processing chip; a dielectric layer over the first active circuit block; a second active circuit block over the dielectric layer, wherein a center of the second active circuit block is offset from a center of the first active circuit block in a direction parallel to a top surface of the central processing chip, the second active circuit block overlaps the first active circuit block in a partial overlap area, and a portion of the first active circuit block extends beyond a boundary of the second active circuit block in a plan view; and a conductive element extending through the dielectric layer, wherein the conductive element electrically connects the first active circuit block to the second active circuit block within the partial overlap area.

19 . The stacked chip layout of claim 18 , further comprising a routing region, wherein a top surface of the routing region is coplanar with a top surface of the first active circuit block, and the conductive element is spaced from the routing region.

20 . The stacked chip layout of claim 19 , wherein a material of the dielectric layer is different from a material of the routing region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Ying-Yu

Classifications

• H01L23/36

  Electricity · mapped topic

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L2225/06548

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic