Method of making stacked chip layout

Patent metadata

Field	Value
Publication number	US-9495500-B2
Application number	US-201514855494-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Aug 30, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A method of making a stacked chip layout includes placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area. The method further includes placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The method further includes placing a third active circuit block over the second active circuit block wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first and second active circuit blocks.

First claim

What is claimed is:

1. A method of making a stacked chip layout, the method comprising:
placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area;
placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block, and a center of the second active circuit block is displaced from a center of the first active circuit block in a first direction parallel to a top surface of the central processing chip; and
placing a third active circuit block over the second active circuit block, the third active circuit block having a fourth area less than the first area, wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, the third active circuit block exposes at least a portion of the first active circuit block and the second active circuit block, and a center of the third active circuit block is displaced from the center of the first active circuit block in a second direction, different from the first direction, parallel to the top surface of the central processing chip.

2. The method of claim 1 , further comprising:
forming a first routing area around the first active circuit block, the first routing area having an area equal to a difference between the second area and the first area;
forming a second routing area around the second active circuit block, the second routing area having an area equal to a difference between the third area and the first area; and
forming a third routing area around the third active circuit block, the third routing area having an area equal to a difference between the fourth area and the first area.

3. The method of claim 2 , further comprising forming a first heat dissipation element in thermal contact with the first active circuit block, the first heat dissipation element extending over a surface of the first routing area.

4. The method of claim 2 , wherein placing the third active circuit block comprises exposes an entirely of the first active circuit block, and
forming the third routing area comprises forming at least one conductive line in the third routing area, the at least one conductive line electrically connecting the third active circuit block to the first active circuit block.

5. The method of claim 1 , further comprising forming a conductive element in an area where the third active circuit block overlaps both the second active circuit block and the first active circuit block, the conductive element configured to transfer a global signal from the central processing chip to each of the first active circuit block, the second active circuit block and the third active circuit block.

6. A method of making a stacked chip layout, the method comprising:
placing a first active circuit block in a first level over a central processing chip, wherein the central processing chip has a first area, and the first active circuit block having a second area less than the first area;
forming a first routing region in the first level, wherein the first routing region has a third area less than the first area;
placing a second active circuit block in a second level over the first level, wherein the second active circuit block has a fourth area less than the first area, and the second active circuit block partially overlaps both the first active circuit block and the first routing region; and
forming a second routing region in the second level, wherein the second routing region has a fifth area less than the first area, and the second routing region partially overlaps both the first active circuit block and the first routing region.

7. The method of claim 6 , further comprising forming an interconnect structure in the second routing region to electrically connect the second active circuit block to the first active circuit block.

8. The method of claim 6 , further comprising forming an interconnect structure in the second routing region to electrically connect the second active circuit block to the central processing chip, wherein the interconnect structure bypasses the first active circuit block.

9. The method of claim 6 , wherein forming the first routing region comprises forming the first routing region to occupy an entirety of the first level except for the second area.

10. The method of claim 6 , wherein forming the second routing region comprises forming the second routing region to occupy an entirety of the second level except for the fourth area.

11. The method of claim 6 , further comprising placing a third active circuit block in a third level over the second level, wherein the third active block has a sixth area less than the first area, and the third active circuit block partially overlaps the first routing region and the second routing region.

12. The method of claim 11 , further comprising forming an interconnect structure through the first routing region and the second routing region to electrically connect the third active circuit block to the first active circuit block.

13. The method of claim 11 , further comprising forming a third routing region in the third level, wherein a combined area of the third routing region and the sixth area is equal to the first area.

14. The method of claim 13 , wherein forming the third routing region comprises forming the third routing region overlapping both the first active circuit block and the second active circuit block.

15. A method of making a stacked chip layout, the method comprising:
placing an active circuit block of a plurality of active circuit blocks over a central processing chip, wherein an area of each active circuit block of the plurality of active circuit blocks is less than an area of the central processing chip;
forming a routing region around a corresponding active circuit block of the plurality of active circuit blocks;
repeating, for each remaining active circuit block of the plurality of active circuit blocks, the placing the active circuit block and the forming the routing region, wherein the plurality of active circuit blocks define a full overlap region where every active circuit block of the plurality of active circuit blocks overlaps every other active circuit block of the plurality of active circuit blocks, and a center of one active circuit block of the plurality of active circuit blocks is displaced from a center of another active circuit block of the plurality of active circuit blocks in two directions parallel to a top surface of the central processing chip; and
forming a global conductive element in the full overlap region, wherein the global conductive element is electrically connected to every active circuit block of the plurality of active circuit blocks.

16. The method of claim 15 , further comprising forming an inter-level via layer over each circuit block of the plurality of active circuit blocks and the routing region for the corresponding active circuit block.

17. The method of claim 16 , further comprising forming a conductive via connecting a first active circuit block of the plurality of active circuit blocks to a second active circuit block of the plurality of active circuit blocks, wherein the conductive via bypasses the routing region corresponding to the first active circuit block and the routing region corresponding to the second active circuit block

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Ying-Yu

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/00

  Package configurations · CPC title