Chip for performing contactless chip test and method for performing contactless chip test on input/output driver

Patent metadata

Field	Value
Publication number	US-2026009844-A1
Application number	US-202519180162-A
Country	US
Kind code	A1
Filing date	Apr 16, 2025
Priority date	Jul 4, 2024
Publication date	Jan 8, 2026
Grant date	—

Abstract

A chip for performing a contactless chip test and a method for performing the contactless chip test on an input/output (IO) driver are provided. The chip includes the IO driver, a receiver and a processor, wherein the IO driver and the receiver are coupled to an IO pad, and the processor is coupled to the IO driver and the receiver. The IO driver drives an IO voltage on the IO pad, and the receiver receives the IO voltage from the IO pad, wherein the receiver includes a reference voltage generator and a comparator, the comparator is coupled to the reference voltage generator. The reference voltage generator provides a reference voltage, and the comparator compares the IO voltage with the reference voltage in order to generate a comparison result. The processor determines whether the IO driver passes the contactless chip test according to the comparison result.

First claim

What is claimed is:

1 . A chip for performing a contactless chip test, comprising:
an input/output (IO) driver, coupled to an IO pad, configured to drive an IO voltage on the IO pad; a receiver, coupled to the IO pad, configured to receive the IO voltage from the IO pad, wherein the receiver comprises:
a reference voltage generator, configured to provide a reference voltage; and
a comparator, coupled to the reference voltage generator, configured to compare the IO voltage with the reference voltage to generate a comparison result; and
a processor, coupled to the IO driver and the receiver, configured to determine whether the IO driver passes the contactless chip test according to the comparison result.

2 . The chip of claim 1 , wherein the IO driver comprises:
a pull up (PU) driver, coupled to the IO pad, configured to pull up the IO voltage; and a pull down (PD) driver, coupled to the IO pad, configured to pull down the IO voltage, wherein the processor is further configured to determine whether each of the PU driver and the PD driver passes the contactless chip test according to the comparison result.

3 . The chip of claim 2 , wherein the contactless chip test comprises a leakage test, and the IO driver further comprises:
an auxiliary PU resistor, coupled to the IO pad, configured to pull up the IO voltage; and an auxiliary PD resistor, coupled to the IO pad, configured to pull down the IO voltage, wherein the processor turns off the PU driver and the PD driver and turns on either the auxiliary PU resistor or the auxiliary PD resistor, to perform the leakage test on the PU driver or the PD driver.

4 . The chip of claim 3 , wherein:
when performing the leakage test on the PU driver, the processor turns on the auxiliary PD resistor and turns off the auxiliary PU resistor, the comparator compares the IO voltage with a first level of the reference voltage to generate a first comparison result, and the processor determines whether the PU driver passes the leakage test according to the first comparison result; and when performing the leakage test on the PD driver, the processor turns on the auxiliary PU resistor and turns off the auxiliary PD resistor, the comparator compares the IO voltage with a second level of the reference voltage to generate a second comparison result, and the processor determines whether the PD driver passes the leakage test according to the second comparison result.

5 . The chip of claim 4 , wherein when the first comparison result indicates that the IO voltage is greater than the first level of the reference voltage, the processor determines that the PU driver fails to pass the leakage test.

6 . The chip of claim 4 , wherein when the second comparison result indicates that the IO voltage is not greater than the second level of the reference voltage, the processor determines that the PD driver fails to pass the leakage test.

7 . The chip of claim 2 , wherein the contactless chip test comprises a voltage level test, the PU driver has multiple PU driving strengths, the PD driver has multiple PD driving strengths, multiple modes of the IO driver respectively correspond to different combinations of the multiple PU driving strengths and the multiple PD driving strengths, and the processor sets the IO driver to the multiple modes by turns, in order to perform the voltage level test on the IO driver.

8 . The chip of claim 7 , wherein the processor is further configured to determine whether the IO voltage falls in a corresponding range under each of the multiple modes of the IO driver according to the comparison result, to determine whether the IO driver passes the voltage level test.

9 . The chip of claim 8 , wherein when the comparison result indicates that the IO voltage falls in the corresponding range under each of the multiple modes of the IO driver, the processor determines that the IO driver passes the voltage level test.

10 . The chip of claim 1 , wherein the IO pad is a micro-bump pad.

11 . A method for performing a contactless chip test on an input/output (IO) driver, wherein the method is applicable to a chip, the chip comprises the IO driver, a receiver and a processor, and the method comprises:
utilizing the IO driver to drive an IO voltage on a IO pad; utilizing the receiver to receive the IO voltage from the IO pad; utilizing a reference voltage generator of the receiver to provide a reference voltage; utilizing a comparator of the receiver to compare the IO voltage with the reference voltage in order to generate a comparison result; and utilizing the processor to determine whether the IO driver passes the contactless chip test according to the comparison result.

12 . The method of claim 11 , wherein the IO driver comprises a pull up (PU) driver and a pull down (PD) driver, the PU driver is configured to pull up the IO voltage, the PD driver is configured to pull down the IO voltage, and utilizing the processor to determine whether the IO driver passes the contactless chip test according to the comparison result comprises:
utilizing the processor to determine whether each of the PU driver and the PD driver passes the contactless chip test according to the comparison result.

13 . The method of claim 12 , wherein the contactless chip test comprises a leakage test, the IO driver further comprises an auxiliary PU resistor and an auxiliary PD resistor, the auxiliary PU resistor is configured to pull up the IO voltage, the auxiliary PD resistor is configured to pull down the IO voltage, and the method further comprises:
utilizing the processor to turn off the PU driver and the PD driver and turn on either the auxiliary PU resistor or the auxiliary PD resistor, to perform the leakage test on the PU driver or the PD driver.

14 . The method of claim 13 , wherein utilizing the processor to turn off the PU driver and the PD driver and turn on either the auxiliary PU resistor or the auxiliary PD resistor to perform the leakage test on the IO driver comprises:
utilizing the processor to turn on the auxiliary PD resistor and turn off the auxiliary PU resistor for performing the leakage test on the PU driver, wherein the comparator compares the IO voltage with a first level of the reference voltage to generate a first comparison result, and the processor determines whether the PU driver passes the leakage test according to the first comparison result; and utilizing the processor to turn on the auxiliary PU resistor and turn off the auxiliary PD resistor for performing the leakage test on the PD driver, wherein the comparator compares the IO voltage with a second level of the reference voltage to generate a second comparison result, and the processor determines whether the PD driver passes the leakage test according to the second comparison result.

15 . The method of claim 14 , further comprising:
in response to the first comparison result indicating that the IO voltage is greater than the first level of the reference voltage, utilizing the processor to determine that the leakage test fails.

16 . The method of claim 14 , further comprising:
in response to the second comparison result indicating that the IO voltage is less than the second level of the reference voltage, utilizing the processor to determine that the leakage test fails.

17 . The method of claim 12 , wherein the contactless chip test comprises a voltage level test, the PU driver has multiple PU driving strengths, the PD driver has multiple PD driving strengths, multiple modes of the IO driver respectively correspond to different combination

Assignees

• Mediatek Inc

Inventors

• Lin Xiang
• Hsieh Ching-Wen
• Huang Han-Jung
• Tseng Jui-Hsing
• Hsu Ying-Yu

Classifications

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/303 Primary

  of integrated circuits (G01R31/305 - G01R31/315 take precedence) · CPC title