Stacked chip layout having overlapped regions

Patent metadata

Field	Value
Publication number	US-10162926-B2
Application number	US-201615291474-A
Country	US
Kind code	B2
Filing date	Oct 12, 2016
Priority date	Aug 30, 2013
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

First claim

What is claimed is:

1. A stacked chip layout comprising:
a central processing chip;
a first active circuit block over the central processing chip;
a second active circuit block over the first active circuit block, wherein a center of the second active circuit block is offset from a center of the first active circuit block in two direction parallel to a top surface of the central processing chip, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block; and
a local conductive element electrically connecting the first active circuit block to the second active circuit block, wherein the local conductive element is within the partial overlap area.

2. The stacked chip layout of claim 1 , wherein the local conductive element extends in a direction perpendicular to a direction of the offset between the center of the first active circuit block and the center of the second active circuit block.

3. The stacked chip layout of claim 1 , further comprising a dielectric layer between the first active circuit block and the second active circuit block.

4. The stacked chip layout of claim 3 , wherein the local conductive element extends through the dielectric layer.

5. The stacked chip layout of claim 1 , further comprising a third active circuit block over the second active circuit block, wherein a first portion of the third active circuit block overlaps both the first active circuit block and the second active circuit block in a full overlap region.

6. The stacked chip layout of claim 5 , wherein the local conductive element in outside of the full overlap region.

7. The stacked chip layout of claim 5 , further comprising an additional local conductive element electrically connecting a second portion of the third active circuit block to the first active circuit block, wherein the second portion of the third active circuit block overlaps the first active circuit block, and the second portion is outside of the full overlap region.

8. The stacked chip layout of claim 7 , wherein the additional local conductive element comprises:
a first segment extending parallel to a direction of the offset from the center of the first active circuit block to the center of the second active circuit block; and
a second segment extending perpendicular to the direction of the offset from the center of the first active circuit block to the center of the second active circuit block.

9. The stacked chip layout of claim 5 , further comprising an additional local conductive element electrically connecting a second portion of the third active circuit block to the first active circuit block, wherein the second portion of the third active circuit block exposes the first active circuit block, and the second portion is outside of the full overlap region.

10. A stacked chip layout comprising:
a central processing chip;
a first active circuit block over the central processing chip;
a second active circuit block over the first active circuit block, wherein the second active circuit block overlaps the first active circuit block, and both the first active circuit block and the second active circuit block are within a perimeter of the central processing chip in a plan view;
a first routing region on a same plane as the second active circuit block;
a second routing region between the first routing region and the first active circuit block; and
a local conductive element electrically connecting the first active circuit block to the second active circuit block, wherein the local conductive element extends through the first routing region and the second routing region.

11. The stacked chip layout of claim 10 , further comprising:
a first dielectric layer in the first routing region, wherein the local conductive element extends through the first dielectric layer; and
a second dielectric layer in the second routing region, wherein the local conductive element extends through the second dielectric layer.

12. The stacked chip layout of claim 10 , wherein the local conductive element is connected to the second active circuit block in a region outside of a portion of the second active circuit block that overlaps the first active circuit block.

13. The stacked chip layout of claim 10 , further comprising a third active circuit block between the first active circuit block and the second active circuit block.

14. The stacked chip layout of claim 13 , wherein the local conductive element is isolated from the third active circuit block.

15. The stacked chip layout of claim 13 , further comprising a full overlap region where the second active circuit block overlaps both the third active circuit block and the first active circuit block.

16. The stacked chip layout of claim 15 , further comprising a global conductive element electrically connected to the first active circuit block, the second active circuit block and the third active circuit block, wherein the global conductive element is in the full overlap region.

17. A stacked chip layout comprising:
a central processing chip;
a first active circuit block over the central processing chip;
a second active circuit block over the first active circuit block, wherein the second active circuit block overlaps the first active circuit block in a partial overlap area, the second active circuit block exposes a portion of the first active circuit block, and the second active circuit block extends beyond at least one edge of the first active circuit block in a plan view; and
a local conductive element electrically connecting the first active circuit block to the second active circuit block, wherein at least a portion of the local conductive element is within the partial overlap area, and the local conductive element is isolated from the central processing chip.

18. The stacked chip layout of claim 17 , wherein the central processing chip comprises a phase locked loop.

19. The stacked chip layout of claim 18 , further comprising a global conductive element electrically connecting the first active circuit block, the second active circuit block and the phase locked loop.

20. The stacked chip layout of claim 19 , wherein the global conductive element is located in a full overlap area, and the full overlap area is a region where the partial overlap area overlaps the central processing chip.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Ying-Yu

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/00

  Package configurations · CPC title