Stacked chip layout and method of making the same

Patent metadata

Field	Value
Publication number	US-10540473-B2
Application number	US-201816206501-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Aug 30, 2013
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

First claim

What is claimed is:

1. A method of making a stacked chip layout, the method comprising:
placing a plurality of active circuit blocks over a central processing chip, wherein the central processing chip has a first area, and each active circuit block of the plurality of active circuit blocks has an area less than the first area; and
forming a plurality of routing regions over the central processing chip; wherein each routing region corresponds to an active circuit block of the plurality of active circuit blocks, each routing region is outside of the corresponding active circuit block and contacts a sidewall of the corresponding active circuit block, and at least one routing region of the plurality of routing regions overlaps with at least another routing region of the plurality of routing regions.

2. The method of claim 1 , further comprising
depositing a dielectric layer over at least one active circuit block of the plurality of active circuit blocks, wherein the dielectric layer is between adjacent active circuit blocks of the plurality of active circuit blocks; and
forming a local conductive element in the dielectric layer to electrically connect the adjacent active circuit blocks of the plurality of active circuit blocks.

3. The method of claim 1 , wherein the forming the plurality of routing regions comprises depositing a dielectric layer on a same level as each active circuit block of the plurality of active circuit blocks.

4. The method of claim 1 , wherein the placing the plurality of active circuit blocks comprises placing each active circuit block of the plurality of active circuit blocks to have a portion which overlaps with every other active circuit block of the plurality of active circuit blocks.

5. The method of claim 4 , further comprising forming a global conductive element extending from the central processing chip through each active circuit block of the plurality of active circuit blocks, wherein the global interconnect extends through the portion of each active circuit block of the plurality of active circuit blocks.

6. The method of claim 1 , further comprising forming a local conductive element electrically connecting a first active circuit block of the plurality of active circuit blocks to a second active circuit block of the plurality of active circuit blocks.

7. The method of claim 6 , wherein the forming the local conductive element comprises forming the local conductive element extending through a routing region of the plurality of routing regions on a same level as the first active circuit block.

8. The method of claim 6 , wherein the forming the local conductive element comprises forming the local conductive element extending through a routing region of the plurality of routing regions on a same level as the second active circuit block.

9. The method of claim 6 , wherein the forming the local conductive element comprises forming the local conductive element extending through a first routing region of the plurality of routing regions on a same level as the first active circuit block and through a second routing region of the plurality of routing regions on a same level as the second active circuit block.

10. The method of claim 6 , wherein the forming the local conductive element comprises forming the local conductive element extending through a routing region of the plurality of routing regions on a different level from each of the first active circuit block and the second active circuit block.

11. A method of making a stacked chip layout, the method comprising:
depositing a first dielectric layer over a central processing chip;
stacking a first active circuit block over the first dielectric layer;
depositing a second dielectric layer over the first active circuit block;
stacking a second active circuit block over the second dielectric layer, wherein the second active circuit block overlaps the first active circuit block in a partial overlap area, the second active circuit block exposes a portion of the first active circuit block, and the second active circuit block extends beyond at least one edge of the first active circuit block in a plan view;
depositing a third dielectric layer over the second dielectric layer, wherein the third dielectric layer is a same distance from the central processing chip as the second active circuit block; and
routing a local conductive element through the third dielectric layer and the second dielectric layer to electrically connect the first active circuit block to the second active circuit block.

12. The method of claim 11 , further comprising routing a global conductive element through the first dielectric layer and the second dielectric layer to electrically connect the second active circuit block to the first active circuit block and to the central processing chip.

13. The method of claim 11 , further comprising stacking a third active circuit block over the second dielectric layer, wherein the third active circuit block is between the first active circuit block and the second active circuit block.

14. The method of claim 13 , further comprising depositing a fourth dielectric layer over the second dielectric layer, wherein the fourth dielectric layer is a same distance from the central processing chip as the third active circuit block.

15. The method of claim 14 , wherein the routing of the local conductive element comprises routing the local conductive element through the fourth dielectric layer.

16. The method of claim 11 , further comprising depositing a fourth dielectric layer over the first dielectric layer, wherein the fourth dielectric layer is a same distance from the central processing chip as the first active circuit block.

17. The method of claim 16 , wherein the routing of the local conductive element comprises routing the local conductive element through the fourth dielectric layer.

18. A method of making a stacked chip layout, the method comprising:
stacking a plurality of circuit block layers over a central processing chip, wherein stacking each of the plurality of circuit block layers comprises:
stacking an active circuit block, and
depositing a dielectric material on a same level as the active circuit block,

wherein the active circuit block of each of the plurality of circuit block layers includes a first portion overlapping the active circuit block of every other circuit block layer of the plurality of circuit block layers, and a second portion exposed by the active circuit block of every other circuit block layer of the plurality of circuit block layers; and
routing a global conductive element electrically connecting the central processing chip to the active circuit block of each of the plurality of circuit block layers, wherein the global conductive element is routed through the first portion of the active circuit block of each of the plurality of circuit block layers.

19. The method of claim 18 , further comprising routing a local conductive element through the dielectric material of a first circuit block layer of the plurality of circuit block layers to electrically connect the active circuit block of the first circuit block layer to the second portion of the active circuit block of a second circuit block layer of the plurality of circuit block layers.

20. The method of claim 18 , wherein the stacking of each of the plurality of circuit block layers comprises depositing a dielectric layer, wherein the stacking of the active circuit block comprises stacking the active circuit block over the deposited dielectric layer, and the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Ying-Yu

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W90/00

  Package configurations · CPC title