Techniques for handling escalation of interrupts in a data processing system
US-11755362-B2 · Sep 12, 2023 · US
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Herrenschmidt Benjamin patents
Herrenschmidt Benjamin is listed as an inventor on 29 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Herrenschmidt Benjamin |
| Total patents | 29 |
| First publication | Apr 30, 2015 |
| Latest publication | Sep 12, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Techniques for handling escalation of interrupts in a data processing system
US-2022398125-A1 · Dec 15, 2022 · US
Process-based virtualization system for executing a secure application process
US-11461474-B2 · Oct 4, 2022 · US
Translation load instruction with access protection
US-11226902-B2 · Jan 18, 2022 · US
Promotion of ERAT cache entries
US-11221957-B2 · Jan 11, 2022 · US
Process-based virtualization system for executing a secure application process
US-2021232693-A1 · Jul 29, 2021 · US
Translation load instruction
US-2021096859-A1 · Apr 1, 2021 · US
Interruptible translation entry invalidation in a multithreaded data processing system
US-10817434-B2 · Oct 27, 2020 · US
Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency
US-10776281-B2 · Sep 15, 2020 · US
Interruptible translation entry invalidation in a multithreaded data processing system
US-2020201780-A1 · Jun 25, 2020 · US
Recent patents
Latest publications not already listed above.
Snoop invalidate filter for distributed memory management unit to reduce snoop invalidate latency
US-2020110710-A1 · Apr 9, 2020 · US
Promotion of erat cache entries
US-2020073817-A1 · Mar 5, 2020 · US
Hardware based isolation for secure execution of virtual machines
US-10387686-B2 · Aug 20, 2019 · US
Configurable I/O address translation data structure
US-10255194-B2 · Apr 9, 2019 · US
Configurable I/O address translation data structure
US-10241923-B2 · Mar 26, 2019 · US
Hardware based isolation for secure execution of virtual machines
US-2019034666-A1 · Jan 31, 2019 · US
Transactional memory system supporting unbroken suspended execution
US-9626187-B2 · Apr 18, 2017 · US
Random number generation security
US-9575728-B1 · Feb 21, 2017 · US
Techniques for improving random number generation security
US-9417846-B1 · Aug 16, 2016 · US
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
US-9330023-B2 · May 3, 2016 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-9323692-B2 · Apr 26, 2016 · US
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
US-9317443-B2 · Apr 19, 2016 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-9311249-B2 · Apr 12, 2016 · US
Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation
US-9251088-B2 · Feb 2, 2016 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-2015301950-A1 · Oct 22, 2015 · US
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
US-2015301953-A1 · Oct 22, 2015 · US
Managing translations across multiple contexts using a tlb with entries directed to multiple privilege levels and to multiple types of address spaces
US-2015301939-A1 · Oct 22, 2015 · US
Managing translations across multiple contexts using a tlb with entries directed to multiple privilege levels and to multiple types of address spaces
US-2015301951-A1 · Oct 22, 2015 · US
Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation
US-2015120985-A1 · Apr 30, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 29 |
| Globalfoundries Inc | 1 |
| Cain Iii Harold W | 1 |
| Frey Bradly G | 1 |
| Herrenschmidt Benjamin | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/1027 | 16 |
| G06F12/1045 | 10 |
| G06F2212/657 | 8 |
| G06F2212/68 | 8 |
| G06F2212/50 | 8 |