Techniques for handling escalation of interrupts in a data processing system

Patent metadata

Field	Value
Publication number	US-11755362-B2
Application number	US-202117345821-A
Country	US
Kind code	B2
Filing date	Jun 11, 2021
Priority date	Jun 11, 2021
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

Techniques of handling interrupt escalation are implemented in hardware. In at least one embodiment, an interrupt presentation controller (IPC) receives an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread. The IPC determines whether the VP thread matches any interruptible VP thread. If not, the IPC conditionally escalates the interrupt requested by the event notification message. Conditionally escalating the interrupt includes determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread. If so, the IPC initiates escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message. If not, the IPC refrains from escalating the interrupt requested by the event notification message.

First claim

What is claimed is:

1. A method of handling interrupt escalation in a data processing system including a processor core that executes virtual processor threads on one or more physical threads of the processor core, the method comprising:
receiving, at an interrupt presentation controller (IPC), an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread;
determining, by the IPC, whether the VP thread referenced in the event notification message matches any interruptible VP thread then available to be interrupted;
based on determining that the VP thread referenced in the event notification message does not match any interruptible VP thread, the IPC conditionally escalating the interrupt requested by the event notification message, wherein the conditionally escalating includes:
the IPC determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread;
based on determining the interrupt priority is greater than the operating priority of said any interruptible VP thread, the IPC initiating escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message; and
based on determining the interrupt priority is not greater than the operating priority of said any interruptible VP thread, the IPC refraining from escalating the interrupt requested by the event notification message.

2. The method of claim 1 , wherein determining, by the IPC, whether the VP thread referenced in the event notification message matches any interruptible VP thread then available to be interrupted includes determining, by the IPC, whether the VP thread referenced in the event notification message matches any interruptible VP thread then available to be interrupted by reference to an interrupt context data structure maintained by the IPC.

3. The method of claim 1 , wherein the conditionally escalating includes:
the IPC conditionally escalating the interrupt only if the event notification message specifies a single target VP thread that is not user-level.

4. The method of claim 2 , and further comprising:
the IPC, based on preemption of a preempted VP thread, transferring a context of the preempted thread from the interrupt context data structure into a VP data structure maintained by the IPC.

5. The method of claim 1 , and further comprising:
maintaining, by an interrupt routing controller, an event notification descriptor data structure including event notification descriptors specifying escalation paths for interrupts; and
based on preemption of a preempted VP thread, the IPC initiating resetting of the escalation path of all event notification descriptors in the event notification descriptor data structure that target the preempted VP thread.

6. The method of claim 1 , and further comprising:
maintaining, by an interrupt source controller in an event assignment data structure, state information indicating whether or not a pending interrupt has been reissued; and
the IPC triggering escalation of one or more pending interrupts that have a sufficient priority and that are indicated by the state information in the event assignment data structure as having been reissued.

7. A data processing system, comprising:
a processor core that executes virtual processor threads on one or more physical threads of the processor core;
an interrupt presentation controller (IPC) coupled to the processor core wherein the IPC is configured to perform:
receiving an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread;
determining whether the VP thread referenced in the event notification message matches any interruptible VP thread then available to be interrupted;
based on determining that the VP thread referenced in the event notification message does not match any interruptible VP thread, conditionally escalating the interrupt requested by the event notification message, wherein the conditionally escalating includes:
the IPC determining whether or not the interrupt priority is greater than the operating priority of any interruptible VP thread;
based on determining the interrupt priority is greater than the operating priority of said any interruptible VP thread, the IPC initiating escalation of the interrupt requested by the event notification message to a next higher software stack level by issuing an escalate message; and
based on determining the interrupt priority is not greater than the operating priority of said any interruptible VP thread, the IPC refraining from escalating the interrupt requested by the event notification message.

8. The data processing system of claim 7 , wherein the IPC determines whether the VP thread referenced in the event notification message matches any interruptible VP thread then available to be interrupted by reference to an interrupt context data structure maintained by the IPC.

9. The data processing system of claim 7 , wherein the conditionally escalating includes:
the IPC conditionally escalating the interrupt only if the event notification message specifies a single target VP thread that is not user-level.

10. The data processing system of claim 8 , wherein the IPC is further configured to perform:
based on preemption of a preempted VP thread, transferring a context of the preempted thread from the interrupt context data structure into a VP data structure maintained by the IPC.

11. The data processing system of claim 7 , and further comprising:
an interrupt routing controller coupled to the IPC, wherein the interrupt routing controller is configured to maintain an event notification descriptor data structure including event notification descriptors specifying escalation paths for interrupts; and
wherein the IPC is configured, based on preemption of a preempted VP thread, to initiate resetting of the escalation path of all event notification descriptors in the event notification descriptor data structure that target the preempted VP thread.

12. The data processing system of claim 7 , and further comprising:
an interrupt source controller coupled to the IPC, wherein the interrupt source controller is configured to maintain, in an event assignment data structure, state information indicating whether or not a pending interrupt has been reissued; and
wherein the IPC is configured to trigger escalation of one or more pending interrupts that have a sufficient priority and that are indicated by the state information in the event assignment data structure as having been reissued.

13. A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, wherein the design structure comprises:
a processor core that executes virtual processor threads on one or more physical threads of the processor core;
an interrupt presentation controller (IPC) coupled to the processor core wherein the IPC is configured to perform:
receiving an event notification message requesting an interrupt, specifying an interrupt priority, and referencing a virtual processor (VP) thread;
determining whether the VP thread referenced in the event notification message matches any interruptible VP thread then available to be interrupted;
based on determining that the VP thread referenced in the event notification message does not match any interruptible VP thread, conditionally escalating the interrupt requested by the event notification message, wherein the conditionally escalating includes:
the IPC determining whether or not

Assignees

• IBM

Inventors

• Auernhammer Florian
• Herrenschmidt Benjamin

Classifications

• G06F9/4818 Primary

  Priority circuits therefor · CPC title