Transactional memory system supporting unbroken suspended execution

Patent metadata

Field	Value
Publication number	US-9626187-B2
Application number	US-78835110-A
Country	US
Kind code	B2
Filing date	May 27, 2010
Priority date	May 27, 2010
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

First claim

What is claimed is:

1. A method, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system comprising:
executing, by a processor of the data processing system, a transaction comprising one or more instructions that modify at least a portion of the transactional memory;
suspending, by the processor, the transaction in response to a transaction suspend instruction being executed by the processor;
executing, by the processor, a suspended block of code of the transaction in a non-transactional manner while the transaction is suspended;
determining, by the processor, if an interrupt occurs while the transaction is suspended and the suspended block of code is executing; and
delaying, by the processor, a transaction abort operation until after the transaction suspension is discontinued and the transaction resumes, in response to an interrupt occurring while the transaction is suspended, wherein the execution of the suspended block of code in a non-transactional manner completes execution without being aborted prior to discontinuing the transaction suspension.

2. The method of claim 1 , further comprising:
storing a pre-transaction program register state in a pre-transaction program register state storage device of the processor in response to execution of the transaction starting; and
storing a copy of a current program register state from program registers in the processor, and a copy of the pre-transactional program register state from the pre-transaction program register state storage device of the processor, in a thread context associated with a thread executing the transaction, in response to determining that an interrupt occurs while the transaction is suspended.

3. The method of claim 2 , further comprising:
resuming the execution of the transaction after the transaction suspension is discontinued; and
generating a lost register checkpoint interrupt in response to resuming the execution of the transaction after the transaction suspension is discontinued based on the transaction abort operation having been delayed, wherein the lost register checkpoint interrupt is an interrupt indicating a resumption of the suspended transaction following an interrupt occurring during execution of the suspended block of code.

4. The method of claim 3 , further comprising:
performing transaction abort handling in response to the lost register checkpoint interrupt being generated, wherein the transaction abort handling comprises rolling-back changes to the transactional memory made by the execution of the transaction prior to the suspending of the transaction, but not changes made to the transactional memory made by execution of the suspended block of code.

5. The method of claim 1 , further comprising:
rescheduling a thread executing the transaction using the pre-transactional program register state from a thread context of the thread after performing transaction abort handling.

6. The method of claim 1 , wherein delaying the transaction abort operation comprises setting a lost register checkpoint interrupt bit in the processor to cause a lost register checkpoint interrupt to be generated when the transaction is resumed and continuing execution of the suspended block of code.

7. The method of claim 1 , wherein a value in a mode register of the processor is set to a value indicating that the processor is operating in a suspended mode of operation in response to suspending the transaction, and wherein determining if an interrupt occurs while the transaction is suspended comprises:
retrieving the value in the mode register in response to the interrupt occurring; and
determining if the retrieved value from the mode register is set to the value indicating that the processor is operating in a suspended mode of operation.

8. The method of claim 2 , further comprising:
storing a flag value in association with contents of the pre-transaction program register state indicating whether the contents of the pre-transaction program register state storage device are valid or invalid, wherein the flag value is set by a process that reclaims facilities associated with the transaction when aborting execution of the transaction, and wherein the flag value is used to resolve race conditions between processes attempting to abort execution of the transaction.

9. The method of claim 1 , wherein:
the data processing system is a multithreaded data processing system executing a sequence of threads comprising at least a first speculative thread and a second speculative thread, and wherein each thread has an associated sequence number specifying its position in the sequence of threads,
the first speculative thread is used to execute the transaction,
the second speculative thread is used to execute a second transaction,
the suspended block of code executes a loop to wait until the second transaction writes the sequence number of the second speculative thread to a variable, monitored by the suspended block of code, indicating that execution of the second transaction has completed execution successfully, and
the execution of the transaction associated with the first speculative thread is resumed in response to the sequence number of the second speculative thread being written to the variable.

10. A method, in a multithreaded data processing system having a processor and a transactional memory, for executing a transaction in the multithreaded data processing system comprising:
executing, by at least one processor of the multithreaded data processing system, a sequence of threads comprising at least a first speculative thread and a second speculative thread, wherein each thread has an associated sequence number specifying its position in the sequence of threads, and wherein the first speculative thread is used to execute a first transaction and the second speculative thread is used to execute a second transaction;
suspending, by the at least one processor, the first transaction in response to a transaction suspend instruction being executed by the at least one processor;
executing, by the at least one processor, a suspended block of code in a non-transactional manner while the first transaction is suspended, wherein the suspended block of code executes a loop to wait until the second transaction writes the sequence number of the second speculative thread to a variable, monitored by the suspended block of code, indicating that execution of the second transaction has completed execution successfully; and
resuming, by the at least one processor, execution of the first transaction associated with the first speculative thread in response to the sequence number of the second speculative thread being written to the variable.

11. A data processing system, comprising:
a processor; and
a transactional memory coupled to the processor, wherein the processor is configured to execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory;
suspend the transaction in response to a transaction suspend instruction being executed by the processor;
execute a suspended block of code of the transaction in a non-transactional manner while the transaction is suspended;
determine if an interrupt occurs while the transaction is suspended and the suspended block of code is executing; and
delay a transaction abort operation until after the transaction suspension is discontinued and the transaction resumes, in response to an interrupt occurring while the transaction is suspended, wherein the execution of the suspended block of code in a non-transactional manner completes execution without being aborted prior to disconti

Assignees

• Cain Iii Harold W
• Frey Bradly G
• Herrenschmidt Benjamin
• Le Hung Q
• May Cathy
• Michael Maged M
• Moreira Jose E
• Nagpurkar Priya A
• Nayar Naresh
• Swanberg Randal C
• IBM

Inventors

• Cain Iii Harold W
• Frey Bradly G
• Herrenschmidt Benjamin
• Le Hung Q
• May Cathy
• Michael Maged M
• Moreira Jose E
• Nagpurkar Priya A
• Nayar Naresh
• Swanberg Randal C

Classifications

• G06F9/30087 Primary

  Synchronisation or serialisation instructions · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title