Promotion of ERAT cache entries

Patent metadata

Field	Value
Publication number	US-11221957-B2
Application number	US-201816119013-A
Country	US
Kind code	B2
Filing date	Aug 31, 2018
Priority date	Aug 31, 2018
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes receiving a request for an Effective Address to Real Address Translation (ERAT); determining whether there is a permissions miss; changing, in response to determining there is a permission miss, permissions of an ERAT cache entry; and providing a Real Address translation. The method, computer program product, and computer system may optionally include providing a promote checkout request to a memory management unit (MMU).

First claim

What is claimed is:

1. A method of processing information in a processor of a computer system, wherein the processor comprises:
a memory management unit (MMU) configured to translate an effective address to a real address, the MMU having a translation-lookaside-buffer (TLB) having a plurality of TLB entries for storing a plurality of Effective Address to Real Address Translations (ERATs); and
an acceleration unit configured to provide an interface between elements on the processor and processing elements external to the processor, the acceleration unit in communication with the MMU and having an ERAT cache having a plurality of ERAT cache entries for storing a plurality of ERATs provided by the MMU, wherein each ERAT cache entry has a corresponding ERAT in an entry in the TLB,
the method comprising:
receiving by the ERAT cache a request for an Effective Address to Real Address Translation (ERAT);
determining whether there is a matching ERAT cache entry in the plurality of ERAT entries in the ERAT cache;
determining whether, in response to there being a matching ERAT cache entry in the ERAT cache, there is an access permissions miss for the matching ERAT cache entry in the ERAT cache;
providing, in response to determining there is an access permissions miss for the matching ERAT cache entry, a promote checkout request to the MMU;
determining whether, in response to providing a promote checkout request to the MMU unit, a promotion of the access permissions for the matching ERAT cache entry is allowed; and
providing, in response to determining the promotion of the access permissions for the matching ERAT entry is not allowed, a promote checkout response containing a fault status to the matching ERAT cache entry;
changing, in response to determining the promotion of the access permissions for the matching ERAT cache entry is allowed, the access permissions of the matching ERAT cache entry in the ERAT cache for which there was the access permissions miss; and
providing a Real Address translation from the matching ERAT cache entry with the changed access permissions in the ERAT cache.

2. The method of claim 1 , wherein the access permission miss occurs when the matching ERAT cache entry is established with read permissions for an Effective Address and a write permission for the Effective Address is received in the request.

3. The method of claim 1 , wherein the request received by the ERAT cache for the ERAT comprises a request for establishing write permission for the ERAT cache entry.

4. The method of claim 1 , wherein the fault status is invoked when the matching ERAT cache entry indicates a write request is not permitted, and the processor sends an interrupt to an operating system of the computer system.

5. The method of claim 1 , wherein changing the access permissions of the ERAT cache entry further comprises changing permissions in the MMU by changing a C bit of a page table entry corresponding to the matching ERAT cache entry, where the C bit indicates the access permissions.

6. The method of claim 1 , wherein changing the permissions of the matching ERAT cache entry further comprises updating the permissions of the matching ERAT cache entry by changing a C bit, where the C bit indicates access permissions.

7. The method of claim 1 , wherein changing the permissions of the matching ERAT cache entry further comprises updating the access permissions of the matching ERAT cache entry from read permission to include either write permission or read/write permission.

8. The method of claim 1 , wherein receiving the request for the ERAT comprises receiving a read request to an address translated by the MMU.

9. The method of claim 1 , further comprising marking an entry in the TLB as in use in response to a translation in the TLB entry residing in an entry in the ERAT cache.

10. A computer program product for a processor, the processor comprising:
a memory management unit (MMU) configured to translate an effective address to a real address, the MMU having a translation-lookaside-buffer (TLB) having a plurality of TLB entries for storing a plurality of Effective Address to Real Address Translations (ERATs); and
an acceleration unit configured to provide an interface between elements on the processor and processing elements external to the processor, the acceleration unit in communication with the MMU and having an ERAT cache having a plurality of ERAT cache entries for storing a plurality of ERATs provided by the MMU, wherein each ERAT cache entry has a corresponding ERAT in an entry in the TLB,
the computer program product comprising:
a non-transitory computer-readable storage medium having program instructions embodied therewith, the program instructions executable by the processor, the program instructions when executed by the processor cause the processor to:
receive by the ERAT cache a request for an Effective Address to Real Address Translation (ERAT);
determine whether there is a matching ERAT cache entry in the ERAT cache storing the plurality of ERATs;
determine whether, in response to there being a matching ERAT cache entry in the ERAT cache, there is an access permissions miss for the matching ERAT cache entry;
determine, in response to determining there is an access permissions miss for the matching ERAT cache entry, whether a promotion of the access permission for the matching ERAT cache entry is allowed; and
changing, in response to determining promotion of the access permission for the matching ERAT cache entry is allowed, the access permissions of the matching ERAT cache entry for which there was the access permission miss without creating a new ERAT cache entry; and
providing a Real Address translation from the matching ERAT cache entry with the changed access permissions in the ERAT cache,
provide, in response to determining the promotion of the access permissions for the matching ERAT cache entry is not allowed, a promote checkout response containing a fault status to the matching ERAT cache entry.

11. The computer program product of claim 10 , further comprising instructions that when executed by the processor cause the processor to:
provide, in response to determining there is an access permission miss for the matching ERAT cache entry, a promote checkout request to the MMU; and
determine whether, in response to providing a promote checkout request to the MMU, a promotion of the access permission for the matching ERAT cache entry is allowed.

12. The computer program product of claim 10 , wherein the request for the ERAT received by the ERAT cache comprises a request for establishing write permission for the ERAT cache entry.

13. The computer program product of claim 10 , wherein changing the access permissions of the matching ERAT cache entry further comprises updating the access permissions of the matching ERAT cache entry from read permission to include either write permission or read/write permission.

14. The computer program product of claim 10 , further comprising instructions that when executed by the processor cause the processor to mark an entry in the TLB as in use in response to a translation in the TLB entry residing in an entry in the ERAT cache.

15. An information handling system comprising:
one or more processors having one or more acceleration units and one or more memory management units (MMUs) wherein at least one of the MMUs is configured to translate an effective address to a real address, the MMU having at least one translation-lookaside-buffer (TLB) having a plurality of TLB entries for storing a plurality of Effective Address to Real Address Translations (ERATs)

Assignees

• IBM

Inventors

• Blaner Bartholomew
• Heaslip Jay G
• Herrenschmidt Benjamin
• Herzl Robert D
• Joyner Jody
• Kriegel Jon K
• Wait Charles D

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/023

  Free address space management · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title