Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer

US9323692B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9323692-B2
Application numberUS-201414255367-A
CountryUS
Kind codeB2
Filing dateApr 17, 2014
Priority dateApr 17, 2014
Publication dateApr 26, 2016
Grant dateApr 26, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space. In response to the TLB controller comparing the virtual address for the current context to a particular entry of at least one entry within the TLB comprising the at least one entry stored for a previous translation of a previous virtual address, the TLB controller only indicates a match between the process identifier field and a translation process identifier field within the particular entry of the TLB if the translation process identifier field is also set to the clamped value.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for managing memory translations, comprising: a processor, coupled with a memory, and configured to perform the actions of: responsive to a current context with a particular process currently in control of the processor requesting access to a shared address space, setting a process identifier field in a virtual address to be looked up in a translation lookaside buffer to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space; and responsive to comparing the virtual address for the current context to a particular entry of at least one entry within the translation lookaside buffer comprising the at least one entry stored for a previous translation of a previous virtual address, only indicating a match between the process identifier field and a translation process identifier field within the particular entry of the translation lookaside buffer if the translation process identifier field is also set to the clamped value. 2. The system according to claim 1 , wherein the processor is further configured to perform the actions of: responsive to the current context requesting access to an application specific space, setting the process identifier field in the virtual address to the identifier for the process; and responsive to comparing the virtual address for the current context to a particular entry of at least one entry within the translation lookaside buffer, indicating a match between the process identifier field and a translation process identifier field within the particular entry of the translation lookaside buffer if the translation process identifier field is set to the identifier for the process. 3. The system according to claim 1 , wherein the processor is further configured to perform the actions of: responsive to comparing the virtual address for the current context to each entry of the at least one entry within the translation lookaside buffer, indicating a match between the effective address field and a translation effective address field within the particular entry if the translation effective address field is set to the address; in response to identifying the particular entry matching both the process identifier field and the effective address field, translating the address using a real page number set in the particular entry; and in responsive to not identifying any entry within the at least one entry matching both the process identifier field and the effective address field, translating the address using at least one page table to identify the translated real page number and adding a new entry to the translation lookaside buffer set to the virtual address and the translated real page number. 4. The system according to claim 1 , wherein the processor is further configured to perform the actions of: receiving, by an AND gate, a first input of the process identifier field and a second input of the translation process identifier field, wherein the AND gate outputs a first value indicating the match if the first input of the process identifier field equals the second input of the translation process identifier field. 5. The system according to claim 1 , wherein the processor is further configured to perform the actions of: responsive to the current context requesting access to a shared address space within a particular logical partition from among a plurality of logical partitions, setting a logical partition identifier field in the virtual address to be looked up in the translation lookaside buffer to a partition identifier for the particular logical partition, wherein the virtual address comprises at least the logical partition identifier field, the process identifier field and the effective address field set to an address in the requested shared address space; and responsive to comparing the virtual address for the current context to a particular entry of at least one entry within the translation lookaside buffer comprising the at least one entry stored for a previous translation of a previous virtual address, identifying a match between the process identifier field and a translation process identifier field within the particular entry if the translation process identifier field is set to the clamped value and identifying a match between the logical partition identifier field and a translation logical partition identifier field within the particular entry if the translation logical partition identifier field is set to the partition identifier. 6. The system according to claim 1 , wherein the processor is further configured to perform the actions of: responsive to the current context for the particular process operating in a highest privilege mode where the highest privilege mode is performed by a virtualization controller that operates in a particular logical partition from among a plurality of logical partitions with access to a core of the processor, setting a logical partition identifier field in the virtual address to be looked up in the translation lookaside buffer to the clamped value different from a partition identifier for the particular logical partition, wherein the virtual address comprises at least the logical partition identifier field, the process identifier field and the effective address field; and responsive to comparing the virtual address for the current context to a particular entry of at least one entry within the translation lookaside buffer comprising the at least one entry stored for a previous translation of a previous virtual address, indicating a match between the logical partition identifier field and a translation logical partition identifier field within the particular entry if the translation logical partition identifier field is set to the clamped value. 7. The system according to claim 1 , wherein the processor is further configured to perform the actions of: responsive to switching control of the processor to a next context with at least one context register value different from the settings of a plurality of context registers for the current context, maintaining each of the at least one entry in the translation lookaside buffer. 8. A computer program product for managing memory translations, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: responsive to a current context with a particular process currently in control of the processor requesting access to a shared address space, set a process identifier field in a virtual address to be looked up in a translation lookaside buffer to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identifier field and an effective address field set to an address in the requested shared address space; and responsive to comparing the virtual address for the current context to a particular entry of at least one entry within the translation lookaside buffer comprising the at least one entry stored for a previous translation of a previous virtual address, only indicate a match between the process identifier field and a translation process identifier field within the particular entry of the translation lookaside buffer if the translation process identifier field is also set to the clamped value. 9. The computer program product according to claim 8 , further comprising the program instructions executable by the processor to cause the processor to: responsive to the current context requesting access to an application specific space, set the proc

Assignees

Inventors

Classifications

  • Details of translation look-aside buffer [TLB] · CPC title

  • Page size control · CPC title

  • Control mechanisms for virtual memory, cache or TLB · CPC title

  • Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

  • TLB miss handling · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9323692B2 cover?
In response to a current context, with a particular process currently in control of a processor requesting access to a shared address space, a translation lookaside buffer (TLB) controller sets a process identifier field in a virtual address to be looked up in a TLB to a clamped value different from an identifier for the process, wherein the virtual address comprises at least the process identi…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F12/1027. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).