Translation load instruction with access protection

Patent metadata

Field	Value
Publication number	US-11226902-B2
Application number	US-201916588380-A
Country	US
Kind code	B2
Filing date	Sep 30, 2019
Priority date	Sep 30, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

A processor core processes a translation load instruction including a protection field specifying a desired access protection to be specified in a translation entry for a memory page. Processing the translation load instruction includes calculating an effective address within the memory page and ensuring that a translation entry containing the desired access protection is stored within at least one translation structure of the data processing system.

First claim

What is claimed is:

1. A method of processing in a data processing system including a system memory, the method comprising:
a processor core processing a translation load instruction, wherein the translation load instruction includes a protection field specifying a desired access protection to be specified in a translation entry for a memory page, and wherein processing the translation load instruction includes:
calculating an effective address within the memory page;
determining that the translation entry containing the desired access protection is stored within at least one translation structure of the data processing system;
and based on determining that the translation entry containing the desired access protection is stored within the at least one translation structure, ending processing of the translation load instruction without further processing of the translation load instruction;

wherein the translation load instruction is unrelated to a data load, data store, or instruction fetch access.

2. The method of claim 1 , wherein:
the at least one translation structure includes a first translation structure in the processor core of a processing unit;
the translation load instruction includes a load field;
the method further comprises the processor core, based on the load field being set, installing the translation entry for the effective address in the first translation structure in the processor core.

3. The method of claim 2 , wherein the first translation structure comprises a translation lookaside buffer.

4. The method of claim 2 , wherein:
the at least one data structure includes a plurality of different translation structures in the processing unit, said plurality of different translation structures including the first translation structure;
and the load field comprises one or more bits, each of the one or more bits individually specifies into which of the plurality of different translation structures the translation entry is to be installed.

5. The method of claim 1 , wherein the at least one translation structure includes a page frame table in the system memory.

6. The method of claim 1 , wherein:
the protection field in the translation load instruction is a first protection field;
the translation entry includes a second protection field;
and the method further comprises the processor core invoking a protection fault handler based on a mismatch of access protections specified in the first and second protection fields.

7. The method of claim 6 , and further comprising:
determining whether a modification of access protections requested by the translation load instruction is legal; and
responsive to determining the modification of access protections requested by the translation load instruction is legal, updating the second protection field in the translation entry.

8. The method of claim 1 , wherein:
the data processing system includes a nest memory management unit coupled to a system fabric of the data processing system;
and the processing comprises the processor core processing the translation load instruction based on receiving an interrupt initiated by the nest memory management unit.

9. A processing unit for a data processing system, the processing unit comprising:
a processor core including:
a memory management unit that translates effective addresses to real addresses;
and an execution unit that executes instructions;

wherein the processor core is configured to perform:
processing a translation load instruction, wherein the translation load instruction includes a protection field specifying a desired access protection to be specified in a translation entry for a memory page, and wherein processing the translation load instruction includes:
calculating an effective address within the memory page;
determining whether the translation entry containing the desired access protection is stored within at least one translation structure of the data processing system;
based on determining the translation entry containing the desired access protection is not stored within the at least one translation structure, loading the translation entry with the desired access protection in the at least one translation structure;
and based on determining the translation entry containing the desired access protection is stored within the at least one translation structure, ending processing of the translation load instruction without further processing of the translation load instruction;

wherein the translation load instruction is unrelated to a data load, data store, or instruction fetch access.

10. The processing unit of claim 9 , wherein:
the at least one translation structure includes a first translation structure in the processor core;
the translation load instruction includes a load field;
the processor core is configured, based on the load field being set, to install the translation entry for the effective address in the first translation structure in the processor core.

11. The processing unit of claim 10 , wherein the first translation structure comprises a translation lookaside buffer.

12. The processing unit of claim 10 , wherein:
the at least one data structure includes a plurality of different translation structures in the processing unit, said plurality of different translation structures including the first translation structure;
and the load field comprises one or more bits, each of the one or more bits individually specifies into which of the plurality of different translation structures the translation entry is to be installed.

13. The processing unit of claim 9 , wherein the at least one translation structure includes a page frame table in the system memory.

14. The processing unit of claim 9 , wherein:
the protection field in the translation load instruction is a first protection field;
the translation entry includes a second protection field; and
the processor core invokes a protection fault handler based on a mismatch of access protections specified in the first and second protection fields.

15. The processing unit of claim 14 , wherein the processor core is further configured to perform:
determining whether a modification of access protections requested by the translation load instruction is legal; and
responsive to determining the modification of access protections requested by the translation load instruction is legal, updating the second protection field in the translation entry.

16. The processing unit of claim 9 , wherein:
the data processing system includes a nest memory management unit coupled to a system fabric of the data processing system; and
the processor core processes the translation load instruction based on receiving, via the system fabric, an interrupt initiated by the nest memory management unit.

17. A data processing system including a plurality of processing units according to claim 9 and a system fabric coupling the plurality of processing units.

18. A program product, comprising:
a computer-readable storage device;
and a design structure stored in the computer-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a processing unit for a data processing system, the processing unit including:
a processor core including:
a memory management unit that translates effective addresses to real addresses;
and an execution unit that executes instructions;

wherein the processing unit is configured to perform:
processing a translation load instruction, wherein the translation load instruc

Assignees

• IBM

Inventors

• Williams Derek E
• Herrenschmidt Benjamin
• May Cathy
• Frey Bradly G

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F2212/206

  Memory mapped I/O · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F12/1441

  for a range · CPC title