Configurable I/O address translation data structure

Patent metadata

Field	Value
Publication number	US-10255194-B2
Application number	US-201314095738-A
Country	US
Kind code	B2
Filing date	Dec 3, 2013
Priority date	Nov 6, 2012
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

First claim

What is claimed is:

1. A method of configuring an input/output (I/O) address translation data structure in a data processing system, the method comprising:
in response to determining to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a processor of the data processing system determining that a first real address range contiguous with an existing TCE data structure in the system memory is not currently unallocated and available for allocation, wherein the existing TCE data structure has a first number of levels;
based on a determination that the first real address range is not currently unallocated and available for allocation, the processor:
determining whether to move a data set from the first real address range-based on at least one input in a set consisting of (1) a priority of a logical partition of a partitionable endpoint in the I/O subsystem for which addresses are translated by reference to the TCE data structure, (2) a type of workload of the logical partition, (3) a priority of a process utilizing the partitionable endpoint, and (4) a utilization percentage of the partitionable endpoint;
based on a determination to move the data set, moving the data set from the first real address range to a third real address range, allocating the first real address range for storage of the TCEs, and retaining the first number of levels in the existing TCE data structure; and
based on a determination not to move the data set, allocating storage for the TCEs in a second real address range discontiguous with the existing TCE data structure and increasing the number of levels in the TCE data structure from the first number to a greater second number.

2. The method of claim 1 , and further comprising:
in response to allocation of the second real address range, updating an I/O device and an I/O bridge in the data processing system with the second number of levels in the TCE data structure.

3. The method of claim 1 , and further comprising:
in response to allocation of the second real address range, setting a pointer in the TCE data structure to point to the second real address range.

4. The method of claim 1 , and further comprising:
based on a determination that the first real address range is currently unallocated and available for allocation, the processor allocating the first real address range for storage of the TCEs and retaining the first number of levels in the TCE data structure.

Assignees

• IBM

Inventors

• Arndt Richard L
• Herrenschmidt Benjamin
• Lais Eric N
• Thurber Steven M

Classifications

• G06F2206/1004

  Defragmentation · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title