Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation

Patent metadata

Field	Value
Publication number	US-9251088-B2
Application number	US-201314066717-A
Country	US
Kind code	B2
Filing date	Oct 30, 2013
Priority date	Oct 30, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Disclosed are computers and methods employing a mechanism for eliminating a race condition between a hypervisor-performed emulation process and a concurrent translation table entry invalidation. Specifically, on a host machine, a hypervisor controls any guest operating systems. In doing so, the hypervisor emulates an instruction by performing a translation operation to acquire a physical address from a virtual address and, if applicable, further from an effective address using translation table(s) (e.g., page tables and, if applicable, segment tables); accesses the physical address; and completes the instruction. During emulation, flagged address table(s) are used to eliminate the race condition. For example, upon receiving an invalidate translation instruction associated with a virtual address, a determination is made as to whether or not the virtual address appears in a flagged virtual address table and, if so, additional action is taken to prevent an error in the translation.

First claim

What is claimed is:

1. A computer comprising:
a processor concurrently executing multiple operating systems comprising at least one guest operating system and a hypervisor;
at least one memory accessible by said processor;
a flag management unit in communication with said processor; and
a flagged virtual address table storing flagged virtual addresses, said flagged virtual address table being stored in any of said flag management unit and said at least one memory and said flag management unit being operably connected to said flagged virtual address table,
said hypervisor performing the following during said concurrently executing:
receiving, from a given guest operating system, a storage access instruction requiring translation of a first virtual address into a physical address in said at least one memory;
transmitting, to said flag management unit, a set flag instruction causing said flag management unit to add said first virtual address to said flagged virtual address table; and
after said transmitting of said set flag instruction, emulating said storage access instruction,

said flag management unit further performing the following during said emulating:
receiving an invalidate translation instruction broadcast by one of said hypervisor and said given guest operating system, said invalidate translation instruction being associated with a second virtual address;
comparing said second virtual address to said flagged virtual addresses stored in said flagged virtual address table; and
when said second virtual address matches said first virtual address, taking additional action to prevent an error in said translation, and

said hypervisor further transmitting, to said flag management unit after said emulating, a clear flag instruction causing said flag management unit to clear said first virtual address from said flagged virtual address table.

2. The computer of claim 1 , further comprising at least one page table stored in said at least one memory and associating virtual addresses with physical addresses in said at least one memory, said emulating comprising:
translating said first virtual address into said physical address using said at least one page table;
accessing said physical address; and
completing said storage access instruction.

3. The computer of claim 1 ,
said additional action by said flag management unit comprising transmitting a conflict notification to said one of said hypervisor and said given guest operating system, and
said one of said hypervisor and said given guest operating system performing any of the following in response to said conflict notification: delaying translation invalidation until said flag is cleared, repeatedly causing said invalidate translation instruction to restart until said flag is cleared and delaying an acknowledgement until said flag is cleared.

4. The computer of claim 3 ,
said one of said hypervisor and said given guest operating system comprising said given guest operating system,
said given guest operating system recognizing a perpetual conflict state and transmitting a forward progress interrupt to said hypervisor when said perpetual conflict state is recognized, and
said hypervisor, in response to said forward progress interrupt, delaying said emulating when said emulating has yet to begin and repeating said emulating when said translation has already occurred.

5. The computer of claim 3 , said one of said hypervisor and said given guest operating system comprising said hypervisor and said hypervisor recognizing a perpetual conflict state and, in response to said perpetual conflict state, delaying said emulating when said emulating has yet to begin and repeating said emulating when said translation has already occurred.

6. The computer of claim 1 , said additional action by said flag management unit comprising delaying translation invalidation until said flag is cleared.

7. The computer of claim 1 ,
said additional action by said flag management unit comprising transmitting a conflict notification to said hypervisor, and
said hypervisor, in response to said conflict notification, delaying said emulating when said emulating has yet to begin and repeating said emulating when said translation has already occurred.

8. A computer comprising:
a processor concurrently executing multiple operating systems comprising at least one guest operating system and a hypervisor;
at least one memory accessible by said processor;
a plurality of translation tables stored in said at least one memory and comprising:
at least one segment table associating effective addresses with virtual addresses; and
at least one page table associating said virtual addresses with physical addresses in said at least one memory; and

a flag management unit in communication with said processor; and
at least one flagged address table storing flagged addresses comprising flagged effective addresses and flagged virtual addresses, said at least one flagged address table being stored in any of said flag management unit and said at least one memory and said flag management unit being operably connected to said at least one flagged address table,
said hypervisor performing the following during said concurrently executing:
receiving, from a given guest operating system, a storage access instruction requiring translation of a first effective address into a physical address in said at least one memory;
transmitting, to said flag management unit, a first set flag instruction causing said flag management unit to add said first effective address to said at least one flagged address table;
after said transmitting of said set first flag instruction, emulating said storage access instruction, said emulating comprising:
translating said first effective address into a first virtual address using said at least one segment table;
transmitting, to said flag management unit, a second set flag instruction, causing said flag management unit to add said first virtual address to said at least one flagged address table;
translating said first virtual address into said physical address using said at least one page table;
accessing said physical address; and
completing said storage access instruction,

said flag management unit further performing the following during said emulating:
receiving an invalidate translation instruction broadcast by one of said hypervisor and said given guest operating system, said invalidate translation instruction being associated with a second address comprising one of a second effective address and a second virtual address;
comparing said second address to said flagged addresses stored in said at least one flagged address table; and
when a match is found between said second address and one of said first effective address and said second effective address, taking additional action to prevent an error in said translation, and

said hypervisor further transmitting, to said flag management unit after said emulating, a clear flags instruction causing said flag management unit to clear said first effective address and said first virtual address from said at least one flagged address table.

9. The computer of claim 8 ,
said additional action by said flag management unit comprising transmitting a conflict notification to said one said hypervisor and said given guest operating system, and
said one of said hypervisor and said given guest operating system performing any of the following in response to said conflict notification: delaying translation invalidation until said flag is cleared, repeatedly causing said invalidate translation instruction to restart until said flag is cleared and delaying an acknowledgement until said flag is cleared.

10. The c

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Frey Bradly G
• Gschwind Michael K
• Herrenschmidt Benjamin

Classifications

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title