Memory array reset read operation
US-12119051-B2 · Oct 15, 2024 · US
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Helm Mark patents
Helm Mark is listed as an inventor on 22 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Helm Mark |
| Total patents | 22 |
| First publication | Mar 17, 2015 |
| Latest publication | Oct 15, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory array reset read operation
US-2022383949-A1 · Dec 1, 2022 · US
Memory array reset read operation
US-11423976-B2 · Aug 23, 2022 · US
Memory array reset read operation
US-2020365201-A1 · Nov 19, 2020 · US
Memory array reset read operation
US-10685702-B2 · Jun 16, 2020 · US
Three dimensional storage cell array with highly dense and scalable word line design approach
US-10593624-B2 · Mar 17, 2020 · US
Memory array reset read operation
US-2019066771-A1 · Feb 28, 2019 · US
Method and apparatus for shielded read to reduce parasitic capacitive coupling
US-10186325-B2 · Jan 22, 2019 · US
Three dimensional storage cell array with highly dense and scalable word line design approach
US-2018331034-A1 · Nov 15, 2018 · US
Apparatus, systems, and methods to operate a memory
US-10090053-B2 · Oct 2, 2018 · US
Recent patents
Latest publications not already listed above.
Method and apparatus for shielded read to reduce parasitic capacitive coupling
US-2018261292-A1 · Sep 13, 2018 · US
Apparatus, systems, and methods to operate a memory
US-2018233200-A1 · Aug 16, 2018 · US
Three dimensional storage cell array with highly dense and scalable word line design approach
US-10043751-B2 · Aug 7, 2018 · US
Apparatus, systems, and methods to operate a memory
US-9972391-B2 · May 15, 2018 · US
Three dimensional storage cell array with highly dense and scalable word line design approach
US-2017287833-A1 · Oct 5, 2017 · US
Method and system to obtain state confidence data using multistrobe read of a non-volatile memory
US-9754683-B2 · Sep 5, 2017 · US
Three dimensional memory control circuitry
US-9620229-B2 · Apr 11, 2017 · US
Apparatus, systems, and methods to operate a memory
US-2016180934-A1 · Jun 23, 2016 · US
Memory program disturb reduction
US-9330777-B2 · May 3, 2016 · US
Three dimensional memory control circuitry
US-9202536-B2 · Dec 1, 2015 · US
Memory program disturb reduction
US-2015170756-A1 · Jun 18, 2015 · US
Memory program disturb reduction
US-8982625-B2 · Mar 17, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 13 |
| Intel Corp | 9 |
| Helm Mark | 3 |
| Kalavade Pranav | 2 |
| Hoei Jung Sheng | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/26 | 18 |
| G11C16/0483 | 15 |
| G11C16/24 | 12 |
| G11C16/3459 | 9 |
| G11C16/3427 | 9 |