Three dimensional storage cell array with highly dense and scalable word line design approach

Patent metadata

Field	Value
Publication number	US-10043751-B2
Application number	US-201615085151-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	Mar 30, 2016
Publication date	Aug 7, 2018
Grant date	Aug 7, 2018

Abstract

An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

First claim

The invention claimed is:

1. An apparatus, comprising:
a three dimensional storage cell array structure;
a staircase structure comprising alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers, the word lines connected to respective storage cells within the three dimensional storage cell array structure; and,
upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure, the upper word lines also connected to second vias that run vertically off a side of the staircase structure other than a front side of the staircase structure, the second vias connected to respective word line driver transistors that are disposed beneath the staircase structure.

2. The apparatus of claim 1 wherein the staircase structure comprises a landing adjacent to a staircase and the second vias run directly off a side of the landing.

3. The apparatus of claim 1 further comprising:
a second staircase structure comprising second alternating conductive and dielectric layers, wherein respective second word lines are formed in the second conductive layers, the second word lines connected to respective storage cells within the three dimensional storage cell array structure; and,
second upper word lines above the second staircase structure that are connected to second first vias that connect to respective steps of the second staircase structure, the second upper word lines also connected to other second vias that run vertically off a side of the second staircase structure other than a front side of the second staircase structure, the other second vias connected to respective word line driver transistors that are disposed beneath the second staircase structure.

4. The apparatus of claim 3 wherein the second staircase structure extends from the staircase structure in a direction away from the three dimensional storage cell array.

5. The apparatus of claim 3 further comprising a second staircase chain that comprises the second staircase structure and the second staircase chain is different than a first staircase chain that comprises the staircase structure.

6. The apparatus of claim 3 wherein the storage cell array structure comprises non volatile memory cells.

7. The apparatus of claim 6 wherein the storage cell array structure comprises any of:
FLASH random access memory (RAM) storage cells;
phase change RAM storage cells;
resistive RAM storage cells;
ferro-electric RAM storage cells;
magnetic RAM storage cells;
spin transfer torque storage cells.

8. A computing system, comprising:
a plurality of processing cores;
a memory controller;
a system memory coupled to the memory controller;
a non volatile storage device;
wherein at least one of the system memory and storage device comprise:
a three dimensional storage cell array structure;
a staircase structure comprising alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers, the word lines connected to respective storage cells within the three dimensional storage cell array structure; and,
upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure, the upper word lines also connected to second vias that run vertically off a side of the staircase structure other than a front side of the staircase structure, the second vias connected to respective word line driver transistors that are disposed beneath the staircase structure.

9. The computing system of claim 8 wherein the staircase structure comprises a landing adjacent to a staircase and the second vias run directly off a side of the landing.

10. The computing system of claim 8 further comprising:
a second staircase structure comprising second alternating conductive and dielectric layers, wherein respective second word lines are formed in the second conductive layers, the second word lines connected to respective storage cells within the three dimensional storage cell array structure; and,
second upper word lines above the second staircase structure that are connected to second first vias that connect to respective steps of the second staircase structure, the second upper word lines also connected to other second vias that run vertically off a side of the second staircase structure other than a front side of the staircase structure, the other second vias connected to respective word line driver transistors that are disposed beneath the second staircase structure.

11. The computing system of claim 10 wherein the second staircase structure extends from the staircase structure in a direction away from the three dimensional storage cell array.

12. The computing system of claim 10 further comprising a second staircase chain that comprises the second staircase structure and the second staircase chain is different than a first staircase chain that comprises the staircase structure.

13. The computing system of claim 10 wherein the storage cell array structure comprises non volatile memory cells.

14. The computing system of claim 13 wherein the storage cell array structure comprises any of:
FLASH random access memory (RAM) storage cells;
phase change RAM storage cells;
resistive RAM storage cells;
ferro-electric RAM storage cells;
magnetic RAM storage cells;
spin transfer torque storage cells.

Assignees

• Intel Corp

Inventors

• Thimmegowda Deepak
• Yip Aaron
• Helm Mark
• Li Yongna

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L27/11578

  Electricity · mapped topic

• H01L21/76816

  Electricity · mapped topic