Memory array reset read operation

Patent metadata

Field	Value
Publication number	US-10685702-B2
Application number	US-201715688645-A
Country	US
Kind code	B2
Filing date	Aug 28, 2017
Priority date	Aug 28, 2017
Publication date	Jun 16, 2020
Grant date	Jun 16, 2020

Abstract

Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

First claim

What is claimed is:

1. A method, comprising:
identifying a part of a read command for setting at least one portion of a memory array to a temporary state;
identifying the at least one portion of the memory array based at least in part on the part of the read command; and
executing the part of the read command on the at least one portion of the memory array based at least in part on identifying the at least one portion of the memory array, wherein executing the part of the read command comprises performing a read recovery part of a read operation.

2. The method of claim 1 , wherein
the read operation comprises the read recovery part and a data sense part, and wherein the read recovery part of the read operation sets the at least one portion of the memory array to the temporary state.

3. The method of claim 1 , further comprising:
increasing a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion;
increasing a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device; and
setting a voltage applied to a source, a drain, a bit line, or a combination thereof, of the at least one portion to a third voltage.

4. The method of claim 3 , further comprising:
decreasing the voltage applied to all word lines from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and
decreasing the voltage applied to the at least one gate of the at least one select gate device from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

5. The method of claim 1 , wherein the temporary state comprises:
a transient state of memory cells of the at least one portion that includes retaining a word line to a channel potential difference of the memory cells at a level that is lower than a voltage of a source, a drain, a bit line, or a combination thereof of the memory cells after executing the part of the read command.

6. The method of claim 1 , further comprising:
determining a duration since a last read operation for the at least one portion, wherein identifying the at least one portion of the memory array is based at least in part on determining the duration.

7. The method of claim 1 , wherein the at least one portion corresponds to a single block of the memory array.

8. The method of claim 1 , further comprising:
determining a mode of executing the part of the read command, wherein executing the part of the read command is based at least in part on determining the mode.

9. The method of claim 8 , further comprising:
identifying a product design identification of the memory array, wherein determining the mode comprises determining a number of portions of the memory array on which the part of the read command is to be executed based at least in part on the product design identification.

10. The method of claim 9 , further comprising:
executing the part of the read command concurrently on a plurality of portions of the memory array based at least in part on determining the number of portions.

11. The method of claim 10 , wherein the plurality of portions comprises a total number of blocks of the memory array.

12. The method of claim 1 , wherein the memory array comprises:
at least one three-dimensional Not-AND (NAND) memory cell.

13. The method of claim 1 , further comprising:
receiving a request to perform the read command; and
initiating the part of the read command based at least in part on receiving the request.

14. The method of claim 13 , further comprising:
identifying a set feature and a trim condition associated with the part of the read command; and
determining a configuration for executing the part of the read command based at least in part on identifying the set feature and the trim condition, wherein executing the part of the read command is based at least in part on determining the configuration.

15. The method of claim 14 , wherein the set feature and the trim condition comprise an execution of the part of the read command on a single block.

16. The method of claim 14 , wherein the set feature and the trim condition comprises an execution of the part of the read command on a maximum number of blocks defined by the trim condition.

17. The method of claim 14 , wherein the set feature and the trim condition comprise an automatic execution of the part of the read command.

18. An apparatus, comprising:
a memory array;
a processor;
a controller coupled with the memory array and the processor, the controller being operable to:
identify a part of a read command for setting at least one portion of a memory array into a temporary state;
identify the at least one portion of the memory array based at least in part on the part of the read command; and
execute the part of the read command on the at least one portion of the memory array, including to perform a read recovery part of a read operation, based at least in part on identifying the at least one portion of the memory array.

19. The apparatus of claim 18 , wherein the controller is further operable to:
determine a number of portions on which the part of the read command is to be executed concurrently based at least in part on a product design identification of the memory array, wherein executing the part of the read command is based at least in part on determining the number of portions.

20. The apparatus of claim 18 , wherein the controller is further operable to:
receive a request from the processor to execute the part of the read command, wherein identifying the part of the read command is based at least in part on the received request.

Assignees

• Micron Technology Inc

Inventors

• Binfet Jeremy
• Helm Mark
• Filipiak William
• Hawes Mark

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1015 Primary

  Read-write modes for single port memories, i.e. having either a random port or a serial port · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title