Memory program disturb reduction

Patent metadata

Field	Value
Publication number	US-9330777-B2
Application number	US-201514632556-A
Country	US
Kind code	B2
Filing date	Feb 26, 2015
Priority date	Aug 31, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

First claim

What is claimed is:

1. A memory device comprising:
a source;
a string of memory cells;
a source select transistor coupled between the string of memory cells and the source;
a source select gate bias circuit configured to apply a first bias voltage value to the source select transistor to electrically isolate the string of memory cells from the source during a first pass of programming and to apply a second bias voltage value to the source select transistor during a second pass of programming; and
a programming circuit configured to apply a programming voltage to a control gate of a first selected memory cell of the string of memory cells during the first pass of programming;
and apply the programming voltage to a control gate of a second selected memory cell of the string of memory cells during the second pass of programming, wherein the first selected memory cell of the string is closer to the source than the second selected memory cell, wherein the programming circuit applies a same programming voltage value during the first pass of programming and the second pass of programming, and wherein first bias voltage value is greater than the second bias voltage value.

2. The memory device of claim 1 , including a verification circuit configured to generate an indication when more than a threshold number of the memory cells of the page failed program verification, wherein the programming circuit is configured to applying the second programming voltage to the access line of the page in response to the indication.

3. The memory device of claim 1 , wherein the programming circuit is configured to apply the programming voltage to an access line of a page of memory cells.

4. A memory device comprising:
a source;
a string of memory cells;
a source select transistor coupled between the string of memory cells and the source;
a source select gate bias circuit configured to apply a first bias voltage value to the source select transistor to electrically isolate the string of memory cells from the source during a first pass of programming and to apply a second bias voltage value to the source select transistor during a second pass of programming; and
a programming circuit configured to apply a programming voltage to a control gate of a first selected memory cell of the string of memory cells during the first pass of programming; and apply the programming voltage to a control gate of a second selected memory cell of the string of memory cells during the second pass of programming, wherein the second selected memory cell of the string is closer to the source select gate than the first selected memory cell of the string, wherein the programming circuit is configured to apply an inhibit voltage to a third memory cell of the string to inhibit programming of the third memory cell, wherein the applied inhibit voltage is greater during the second programming pass than the first programming pass, and wherein the first bias voltage value is less than the second bias voltage value.

5. The memory device of claim 4 , including a verification circuit configured to generate an indication when more than a threshold number of the memory cells of the page failed program verification, wherein the programming circuit is configured to applying the second programming voltage to the access line of the page in response to the indication.

6. The memory device of claim 4 , wherein the programming circuit is configured to perform an intervening programming pass between the first programming pass and the second programming pass.

7. A memory device comprising:
a source;
a string of memory cells;
a source select transistor coupled between the string of memory cells and the source;
a source select gate bias circuit configured to apply a first bias voltage value to the source select transistor to electrically isolate the string of memory cells from the source during a first pass of programming and to apply a second bias voltage value to the source select transistor during a second pass of programming; and
a programming circuit configured to apply a programming voltage to a control gate of a first selected memory cell of the string of memory cells during the first pass of programming;
and apply the programming voltage to a control gate of a second selected memory cell of the string of memory cells during the second pass of programming, wherein the first selected memory cell is located in a different position with respect to the source select gate than the second selected memory cell, and wherein the second bias voltage value is different from the first bias voltage value.

8. The memory device of claim 7 , wherein the second bias voltage value is greater than the first bias voltage value, and wherein the source gate select bias circuit is configured step the bias voltage is stepped from the first bias voltage value to the second bias voltage value.

9. The memory device of claim 7 , wherein the programming circuit is configured to perform the first and second passes of programming among multiple passes of programming, and wherein source gate select bias circuit is configured to monotonically increase the bias voltage value applied to the source select gate during the multiple programming passes.

10. A memory device comprising:
a source;
a string of memory cells;
a source select transistor coupled between the string of memory cells and the source;
a source select gate bias circuit configured to apply a first bias voltage value to the source select transistor to electrically isolate the string of memory cells from the source during a first pass of programming and to apply a second bias voltage value to the source select transistor during a second pass of programming; and
a programming circuit configured to apply a programming voltage to a control gate of a selected memory cell of the string of memory cells, wherein the string of memory cells is a vertical NAND string in a three-dimensional array of memory cells.

11. The memory device of claim 10 , wherein the control gate is electrically connected to an access line of a page of memory cells, and wherein the programming circuit is configured to apply the programming voltage to the access line during a first pass of programming, and apply a second different programming voltage to the access line during the second pass of programming.

12. The memory device of claim 11 , wherein the programming circuit is configured to apply the programming voltage to the access line during a first pass of programming, and apply a second greater programming voltage to the access line during the second pass of programming, and wherein the source gate select bias circuit is configured to apply the first bias voltage value to the source select transistor during the first pass of programming and to apply a second bias voltage value greater than the first bias voltage to the source select transistor during the second pass of programming.

13. The memory device of claim 11 , wherein the programming circuit is configured to step the programming voltage from a first programming voltage value to a second programming voltage value for the second programming pass, and wherein the source gate select bias circuit is configured step the bias voltage is stepped from the first bias voltage value to the second bias voltage value for the second programming pass.

14. The memory device of claim 11 , wherein the programming circuit is configured to perform the first and second passes of programming among multiple passes of programming, and wherein source gate select bias circuit is configured to monotonically increase the bias voltage value applied to the source sele

Assignees

• Micron Technology Inc

Inventors

• Goda Akira
• Helm Mark
• Kalavade Pranav
• Srinivasan Charan

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/30

  Power supply circuits · CPC title