Three dimensional memory control circuitry

Patent metadata

Field	Value
Publication number	US-9620229-B2
Application number	US-201514926401-A
Country	US
Kind code	B2
Filing date	Oct 29, 2015
Priority date	Mar 26, 2012
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate having a back surface extending in an X dimension and a Y dimension;
a three-dimensional memory array comprising vertical memory cells extending in a Z direction from the back surface of the substrate;
a first control circuit built on the substrate and positioned at least partially under a first quadrant of the three-dimensional memory array;
a first set of control lines coupled to the first control circuit through vias that pass through at least one level of the three-dimensional memory array in the Z direction, coupled to the first quadrant of the three-dimensional memory array, and coupled to a second quadrant of the three-dimensional memory array;
a second control circuit built on the substrate and positioned at least partially under the second quadrant of the three-dimensional memory array; and
a second set of control lines coupled to the second control circuit, coupled to the second quadrant of the three-dimensional memory array, and coupled to a third quadrant of the three-dimensional memory array.

2. The integrated circuit of claim 1 , wherein the first set of control lines are substantially perpendicular to the second set of control lines.

3. The integrated circuit of claim 1 , wherein the vertical memory cells comprise NAND memory cells, floating gate flash memory cells, charge-trap flash memory cells, phase-change memory cells, resistive memory cells or ovonic memory cells.

4. The integrated circuit of claim 1 , wherein the three-dimensional memory array of vertical memory cells comprises:
a silicon body coupled to a source line at a bottom portion thereof and to a bit line at a top portion thereof;
a source control gate controlled by the source control line; and
a drain control gate controlled by a drain control line.

5. The integrated circuit of claim 1 , wherein the first control circuit comprises line driver circuitry.

6. The integrated circuit of claim 1 , wherein the second control circuit comprises sense amplifier circuitry.

7. The integrated circuit of claim 1 , wherein a majority of the first control circuit is positioned under the first quadrant of the three-dimensional memory array.

8. The integrated circuit of claim 1 , further comprising:
a third control circuit built on the substrate and positioned at least partially under the third quadrant of the three-dimensional memory array;
a third set of control lines coupled to the third control circuit through vias that pass through at least one level of the three-dimensional memory array in the Z direction, coupled to the third quadrant of the three-dimensional memory array, and coupled to a fourth quadrant of the three-dimensional memory array;
a fourth control circuit built on the substrate and positioned at least partially under the fourth quadrant of the three-dimensional memory array; and
a fourth set of control lines coupled to the fourth control circuit, coupled to the fourth quadrant of the three-dimensional memory array, and coupled to the first quadrant of the three-dimensional memory array.

9. The integrated circuit of claim 8 , wherein the first set of control lines are substantially parallel to the third set of control lines, and substantially perpendicular to the second and fourth sets of control lines.

10. The integrated circuit of claim 8 , comprising:
the first set of control lines and the third set of control lines are word lines; and
the second set of control lines and the fourth set of control lines are bit lines.

11. The integrated circuit of claim 10 , comprising:
the first control circuit and the third control circuit are line driver circuitry; and
the second control circuit and the fourth control circuit are sense amplifier circuitry.

12. The integrated circuit of claim 4 , comprising:
the first set of control lines are word lines; and
the three-dimensional memory array including a number, N, of vertical memory cells, each of the vertical memory cells is coupled to at least one of the word lines.

13. An electronic system comprising:
a processor to generate memory control commands; and
a memory device coupled with the processor, the memory device includes:
a substrate having a back surface extending in an X dimension and a Y dimension;
a three-dimensional memory array comprising vertical memory cells extending in a Z direction from the back surface of the substrate;
a first control circuit built on the substrate and positioned at least partially under a first quadrant of the three-dimensional memory array;
a first set of control lines coupled to the first control circuit through vias that pass through at least one level of the three-dimensional memory array in the Z direction, coupled to the first quadrant of the three-dimensional memory array, and coupled to a second quadrant of the three-dimensional memory array;
a second control circuit built on the substrate and positioned at least partially under the second quadrant of the three-dimensional memory array; and
a second set of control lines coupled to the second control circuit, coupled to the second quadrant of the three-dimensional memory array, and coupled to a third quadrant of the three-dimensional memory array.

14. The electronic system of claim 13 , wherein the first set of control lines are substantially perpendicular to the second set of control lines.

15. The electronic system of claim 13 , wherein the vertical memory cells comprise NAND memory cells, floating gate flash memory cells, charge-trap flash memory cells, phase-change memory cells, resistive memory cells or ovonic memory cells.

16. The electronic system of claim 13 , wherein the three-dimensional memory array of vertical memory cells comprises:
a silicon body coupled to a source line at a bottom portion thereof and to a bit line at a top portion thereof;
a source control gate controlled by the source control line; and
a drain control gate controlled by a drain control line.

17. The electronic system of claim 16 , comprising:
the first set of control lines are word lines; and
the three-dimensional memory array including a number, N, of vertical memory cells, each of the vertical memory cells is coupled to at least one of the word lines.

18. The electronic system of claim 13 , wherein the first control circuit comprises line driver circuitry.

19. The electronic system of claim 13 , wherein the second control circuit comprises sense amplifier circuitry.

20. The electronic system of claim 13 , wherein a majority of the first control circuit is positioned under the first quadrant of the three-dimensional memory array.

21. The electronic system of claim 13 , further comprising:
a third control circuit built on the substrate and positioned at least partially under the third quadrant of the three-dimensional memory array;
a third set of control lines coupled to the third control circuit through vias that pass through at least one level of the three-dimensional memory array in the Z direction, coupled to the third quadrant of the three-dimensional memory array, and coupled to a fourth quadrant of the three-dimensional memory array;
a fourth control circuit built on the substrate and positioned at least partially under the fourth quadrant of the three-dimensional memory array; and
a fourth set of control lines coupled to the fourth control circuit, coupled to the fourth quadrant of the three-dimensional memory array, and coupled to the first quadrant of the three-dimensiona

Assignees

• Intel Corp

Inventors

• Helm Mark
• Hoei Jung Sheng
• Yip Aaron
• Nguyen Dzung

Classifications

• G11C7/18 Primary

  Bit line organisation; Bit line lay-out · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H01L27/1052

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• G11C13/0023

  Address circuits or decoders · CPC title