Apparatus, systems, and methods to operate a memory

Patent metadata

Field	Value
Publication number	US-9972391-B2
Application number	US-201514971634-A
Country	US
Kind code	B2
Filing date	Dec 16, 2015
Priority date	Dec 17, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

First claim

What is claimed is:

1. A method of operating a memory, the method comprising:
selecting a block of a three-dimensional memory, a string of a plurality of strings in the selected block, and a memory cell of the selected string, and
reading a logic level in the selected memory cell by sensing the logic level in response to a read current flowing from a common region through the selected string to a data line with the common region at a higher voltage than the data line.

2. The method of claim 1 , wherein the method includes precharging channels of each string of the plurality of strings in the selected block to read the logic level in the selected memory cell and, after precharging, applying read related signals such that a transistor, in each unselected string that couples the unselected string to the common region, is rendered non-conductive.

3. The method of claim 1 , wherein the method includes using supply voltages Vcc and Vss, Vcc>Vss, in a precharging of the plurality of strings and in the reading of the logic level in the selected memory cell such that Vcc is applied to the common region during the precharging and during the reading, and Vss is applied to the common region after the reading.

4. The method of claim 1 , wherein the method includes conducting a precharge followed by the reading of the logic level in the selected memory cell by applying a precharge voltage, Vpre, to the data line during the precharge and applying a supply voltage, Vcc, to the common region during the precharge, Vcc>Vpre.

5. The method of claim 1 , wherein the method includes conducting operation of a three-dimensional memory having the plurality of strings equal 16 strings and having 32 tiers of control gate lines, each control gate line of each tier coupled to a respective control gate in each of the 16 strings.

6. A method of operating a memory, the method comprising:
precharging channels of each string of a plurality of strings in a selected block of a three-dimensional memory from a common region to each string of the plurality of strings;
applying a pass_read voltage to unselected control gates of the plurality of strings; and
applying a read voltage to a selected control gate of a selected string of the plurality of strings while applying the pass_read voltage to the unselected control gates such that voltage of channels of unselected strings are boosted and read current flows from the common region through channels of the selected string to a data line with the common region at a higher voltage than the data line.

7. The method of claim 6 , wherein precharging includes applying a voltage to the unselected control gates, the selected control gate, and the common region at a level greater than a voltage level applied to the data line for precharging.

8. The method of claim 7 , wherein applying the voltage to the unselected control gates, the selected control gate, and the common region includes applying supply voltage Vcc to the unselected control gates, the selected control gate, and the common region with supply voltage Vss or a precharge voltage applied to the data line, Vcc being greater than Vss and greater than the precharge voltage.

9. The method of claim 6 , wherein the method includes reading a logic one at the data line having a voltage higher than voltage at the data line reading a logic zero.

10. The method of claim 6 , wherein the method includes programming memory cells of a string of the plurality of strings in a program cell order from the data line to the common region.

11. An apparatus comprising:
a three-dimensional memory having a block of memory cells;
a plurality of strings in the block arranged with each string of the plurality of strings coupled to a data line and to a common region, each string including a plurality of memory cell transistors, each memory cell transistor having a control gate and a channel, each string coupled to the data line individually by a select transistor and each string individually coupled to the common region by a source select transistor;
control circuitry to operatively apply read related signals to the plurality of strings such that a string of the plurality of strings is operatively selected and a memory cell of the selected string is operatively selected to read the selected memory cell; and
a sense amplifier configured to read a logic level in the selected memory cell in response to a read current flowing from the common region through the selected string to the data line with the common region at a higher voltage than the data line.

12. The apparatus of claim 11 , wherein the control circuitry is structured to operatively precharge channels of each string of the plurality of strings in the block to read the logic level in the selected memory cell and, after the precharge, to apply the read related signals such that the source select transistor in each unselected string is rendered non-conductive.

13. The apparatus of claim 11 , wherein the control circuitry is structured to apply a supply voltage Vcc to the common region during a precharge of the plurality of strings and during the read of the selected memory cell, and to apply a supply voltage Vss to the common region after the read, Vcc>Vss.

14. The apparatus of claim 13 , wherein the control circuitry is structured to apply a precharge voltage, Vpre, to the data line during the precharge.

15. The apparatus of claim 11 , wherein the data line is coupled to a low supply voltage, Vss, by an n-type metal oxide semiconductor load transistor.

16. The apparatus of claim 11 , wherein the apparatus includes a verify circuit for each memory cell, the verify circuit having a node at the output of a flip-flop coupled to a load transistor disposed in a path to the input of the flip-flop.

17. An apparatus comprising:
a three-dimensional memory having a block of memory cells;
a plurality of strings in the block arranged with each string of the plurality of strings coupled to a data line and to a common region, each string including a plurality of memory cell transistors, each memory cell transistor having a control gate and a channel, each string coupled to the data line individually by a select transistor and each string individually coupled to the common region by a source select transistor;
control circuitry structured to operatively select a string of the plurality of strings and select a memory cell via the control gate of the selected memory cell in the selected string, to operatively precharge channels of each string of the plurality of strings in the block from the common region, to apply a pass_read voltage to unselected control gates of the plurality of strings, and to operatively apply a read voltage to the selected control gate during application of the pass_read voltage to the unselected control gates such that voltage of channels of unselected strings are boosted and read current flows from the common region through channels of the selected string to the data line; and
a sense amplifier configured to read a logic level in the selected memory cell in response to the read current flowing from the common region through the selected string to the data line with the common region at a higher voltage than the data line.

18. The apparatus of claim 17 , wherein the control circuitry is structured to conduct the precharge by application of a voltage to the unselected control gates, the selected control gate, and the common region at a level greater than a voltage level applied to the data line in the precharge.

19. The apparatus of claim 18 , whe

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji
• Hasegawa Takehiro
• Helm Mark

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/24

  Bit-line control circuits · CPC title