Memory array reset read operation

Patent metadata

Field	Value
Publication number	US-11423976-B2
Application number	US-202016896750-A
Country	US
Kind code	B2
Filing date	Jun 9, 2020
Priority date	Aug 28, 2017
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

First claim

What is claimed is:

1. A method, comprising:
initiating a reset read operation that sets at least one portion of a memory array into a temporary state, wherein a full read operation that is different than the reset read operation comprises a read recovery part and a data sense part, and wherein the reset read operation comprises the read recovery part of the full read operation;
applying, to all word lines associated with the at least one portion, a voltage that increases to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;
applying, to at least one gate of at least one select gate device of the at least one portion, a voltage that increases to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and
setting a node of the at least one portion to a third voltage based at least in part on the initiating.

2. The method of claim 1 , wherein the reset read operation that sets the at least one portion of the memory array into the temporary state comprises:
initiating a transition of the at least one portion into the temporary state.

3. The method of claim 1 , wherein the reset read operation that sets the at least one portion of the memory array into the temporary state comprises:
maintaining the at least one portion in the temporary state.

4. The method of claim 1 , wherein the node comprises a source, a drain, a bit line, or a combination thereof.

5. The method of claim 1 , further comprising:
decreasing the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and
decreasing the voltage applied to the at least one gate of the at least one select gate device of the at least one portion from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

6. The method of claim 5 , wherein:
the first voltage is higher than the second voltage;
the second voltage is higher than the third voltage; and
the third voltage is a ground potential.

7. A method, comprising:
initiating a reset read command that sets at least one portion of a memory array into a temporary state;
applying, to all word lines associated with the at least one portion, a voltage that increases to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;
applying, to at least one gate of at least one select gate device of the at least one portion, a voltage that increases to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and
setting a node of the at least one portion to a third voltage based at least in part on the initiating, wherein:
the reset read command comprises a read recovery part of a read operation,
the read operation comprises the read recovery part and a data sense and transfer part, and
the read recovery part comprises applying the voltage that increases to the first voltage above the threshold voltage of the memory cells, applying the voltage that increases to the second voltage above the second threshold voltage of the at least one select gate device, and setting the node of the at least one portion to the third voltage.

8. An apparatus, comprising:
a memory array;
a controller coupled with the memory array, the controller being operable to cause the apparatus to:
initiate a reset read operation that sets at least one portion of a memory array into a temporary state, wherein a full read operation that is different than the reset read operation comprises a read recovery part and a data sense part, and wherein the reset read operation comprises the read recovery part of the full read operation;
increase a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;
increase a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and
set a node of the at least one portion to a third voltage based at least in part on the initiating.

9. The apparatus of claim 8 , wherein, to execute the reset read operation that sets the at least one portion of the memory array into the temporary state, the controller is further operable to cause the apparatus to:
initiate a transition of the at least one portion into the temporary state.

10. The apparatus of claim 8 , wherein, to execute the reset read operation that sets the at least one portion of the memory array into the temporary state, the controller is further operable to cause the apparatus to:
maintain the at least one portion in the temporary state.

11. The apparatus of claim 8 , wherein the controller is further operable to cause the apparatus to:
decrease the voltage applied to all word lines associated with the at least one portion from the first voltage to a fourth voltage based at least in part on achieving the first voltage; and
decrease the voltage applied to the at least one gate of the at least one select gate device of the at least one portion from the second voltage to below the second threshold voltage based at least in part on decreasing the voltage applied to all word lines.

12. The apparatus of claim 11 , wherein:
the first voltage is higher than the second voltage;
the second voltage is higher than the third voltage; and
the third voltage is a ground potential.

13. The apparatus of claim 8 , wherein the node comprises a source, a drain, a bit line, or a combination thereof.

14. The apparatus of claim 8 , wherein the controller is further operable to cause the apparatus to:
identify a set feature and a trim condition associated with the reset read operation; and
determine a configuration for performing the reset read operation based at least in part on identifying the set feature and the trim condition.

15. The apparatus of claim 14 , wherein the set feature and the trim condition are operable to be set by a processor coupled with the controller.

16. An apparatus, comprising wherein:
a memory array;
a controller coupled with the memory array, the controller being operable to cause the apparatus to:
initiate a reset read command that sets at least one portion of a memory array into a temporary state;
increase a voltage applied to all word lines associated with the at least one portion to a first voltage above a threshold voltage of memory cells of the at least one portion based at least in part on the initiating;
increase a voltage applied to at least one gate of at least one select gate device of the at least one portion to a second voltage above a second threshold voltage of the at least one select gate device based at least in part on the initiating; and
set a node of the at least one portion to a third voltage based at least in part on the initiating, wherein:
executing the reset read command comprises performing a read recovery part of a read operation;
the read operation comprises the read recovery part and a data sense and transfer part; and
to execute the read recovery part, the controller is further operable to cause the apparatus to:
apply the voltage that increases to the first voltage abo

Assignees

• Micron Technology Inc

Inventors

• Binfet Jeremy
• Helm Mark
• Filipiak William
• Hawes Mark

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C7/1015 Primary

  Read-write modes for single port memories, i.e. having either a random port or a serial port · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title