Method and system to obtain state confidence data using multistrobe read of a non-volatile memory

Patent metadata

Field	Value
Publication number	US-9754683-B2
Application number	US-201213977011-A
Country	US
Kind code	B2
Filing date	Mar 29, 2012
Priority date	Mar 29, 2012
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1. An apparatus, comprising:
a processor circuit to retrieve data from a non-volatile memory; and
a multistrobe read module operable on the processor circuit to:
set a read operation to read a memory cell over a multiplicity of sense operations, each sense operation of the multiplicity of sense operations performed under a different sense condition, the memory cell comprising a wordline;
determine a state of the read operation subsequent a current sense operation;
determine whether the state of the read operation subsequent the current sense operation is within a preset range; and
schedule a next sense operation to succeed the current sense operation of the multiplicity of sense operations without recharge of the wordline based on a determination that the state of the read operation is within the preset range, and with recharge of the wordline based on a determination that the state of the read operation is not within the preset range.

2. The apparatus of claim 1 , the multistrobe read module operable to selectively adjust one or more read parameters to be applied to read data from the memory cell based upon an error rate of data read by performing the multiplicity of sense operations, the one or more read parameters including state of a bitline discharge path of the non-volatile memory, wordline voltage level of a wordline to read the memory cell of the non-volatile memory, and precharge level of the bitline.

3. The apparatus of claim 2 , the multistrobe read module operable on the processor circuit to:
send results of the multiplicity of sense operations for storing as encoded state confidence data; and
schedule the stored encoded state confidence data to be sent to an external device only after completion of the multiplicity of sense operations.

4. The apparatus of claim 2 , the multistrobe read module operable on the processor circuit to disable the bitline discharge path when a duration of ramping of the wordline between consecutive sense operations exceeds a first threshold.

5. The apparatus of claim 2 , the multistrobe read module operable on the processor circuit to adjust wordline voltage when a difference between a state of the wordline that existed when verifying placement of the memory cell and an expected state of the wordline for a subsequent read operation exceeds a second threshold.

6. The apparatus of claim 2 , the multistrobe read module operable on the processor circuit to direct the precharge level of the bitline to be adjusted and the bitline refilled when time allocated to adjust wordline voltage between a first sense operation and a next sense operation exceeds a third threshold.

7. The apparatus of claim 2 , the multistrobe module operable to direct the precharge level of the bitline to be adjusted and the bitline refilled between a first sense operation and a next sense operation when an offset between bitline read and bitline verify conditions exceeds a fourth threshold.

8. The apparatus of claim 1 , the multistrobe module operable on the processor circuit to adjust, when a variation in bitline voltage during the read operation exceeds a fifth threshold, one or more of a value of a reference voltage to be used during a sense pulse of a sense operation, and a duration of the sense pulse.

9. The apparatus of claim 1 , the multistrobe module operable on the processor circuit to adjust one or more of a value of a reference voltage to be used during a sense pulse of a sense operation, and a duration of the sense pulse when a variation in wordline voltage during the read operation exceeds a sixth threshold.

10. The apparatus of claim 1 , comprising a digital display to present results of data read from the non-volatile memory.

11. A computer implemented method, comprising:
performing a multistrobe read operation that comprises:
setting a read operation to read a memory cell of a non-volatile memory over a multiplicity of sense operations, each sense operation of the multiplicity of sense operations to be performed under a different sense condition, the memory cell comprising a wordline;
determining a state of the read operation subsequent a current sense operation;
determining whether the state of the read operation subsequent the current sense operation is within a preset range; and
scheduling a next sense operation to succeed the current sense operation of the multiplicity of sense operations without recharge of the wordline based on a determination that the state of the read operation is within the preset range, and with recharge of the wordline based on a determination that the state of the read operation is not within the preset range.

12. The computer implemented method of claim 11 , comprising selectively adjusting one or more read parameters to be applied to read data from the non-volatile memory based upon an error rate of data read by performing the multiplicity of sense operations, the one or more read parameters including state of a bitline discharge path of the non-volatile memory, wordline voltage level of a wordline to read the memory cell of the non-volatile memory, and precharge level of the bitline.

13. The computer implemented method of claim 12 , comprising:
sending results of the multiplicity of sense operations for storing as encoded state confidence data, each sense condition comprising a combination of sense voltage and sense pulse duration; and
scheduling the stored encoded state confidence data to be sent to an external device only after completion of the multiplicity of sense operations.

14. The computer implemented method of claim 12 , comprising disabling the bitline discharge path when a duration of ramping of the wordline between consecutive sense operations exceeds a first threshold.

15. The computer implemented method of claim 12 , comprising adjusting wordline voltage when a difference between a state of the wordline that existed when verifying placement of the memory cell and an expected state of the wordline for a subsequent read operation exceeds a second threshold.

16. The computer implemented method of claim 12 , comprising directing the precharge level of the bitline to be adjusted and the bitline to be refilled when time allocated to adjust wordline voltage between a first sense operation and a next sense operation exceeds a third threshold.

17. The computer implemented method of claim 12 , comprising directing the precharge level of the bitline to be adjusted and the bitline refilled between a first sense operation and a next sense operation when an offset between bitline read and bitline verify conditions exceeds a fourth threshold.

18. The computer implemented method of claim 11 , comprising adjusting one or more of a value of a reference voltage to be used during a sense pulse of a sense operation, and a duration of the sense pulse when a variation in wordline voltage during the read operation exceeds a fifth threshold.

19. At least one non-transitory computer-readable storage medium comprising a plurality of instructions that, when executed, cause a system to:
set a read operation to read a memory cell of a non-volatile memory over a multiplicity of sense operations, each sense operation of the multiplicity of sense operations to be performed under a different sense condition, the memory cell comprising a wordline;
determine a state of the read operation subsequent a current sense operation;
determine whether the state of the read operation subsequent the current sense operation is within a preset range; and
schedule a next sense operation

Assignees

• Goldman Matthew
• Parat Krishna K
• Kalavade Pranav
• Franklin Nathan R
• Helm Mark
• Intel Corp

Inventors

• Goldman Matthew
• Parat Krishna K
• Kalavade Pranav
• Franklin Nathan R
• Helm Mark

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/5004

  Voltage · CPC title