Method and apparatus for shielded read to reduce parasitic capacitive coupling

Patent metadata

Field	Value
Publication number	US-10186325-B2
Application number	US-201715451777-A
Country	US
Kind code	B2
Filing date	Mar 7, 2017
Priority date	Mar 7, 2017
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

First claim

What is claimed is:

1. An apparatus comprising:
a NAND flash memory device comprising a memory device controller and a NAND flash memory array, the NAND flash memory device to:
program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines;
couple the first plurality of bitlines to a fixed bias voltage in response to a first read command;
select one of a stepped architecture and a ramped architecture of the NAND flash memory device to apply one or more read voltages to the wordline in response to the first read command, the selection performed by the NAND flash memory device based on a number of sense operations to be performed during performance of the first read command;
apply the one or more read voltages to the wordline coupled to the plurality of NAND flash memory cells via the selected stepped or ramped architecture; and
sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

2. The apparatus of claim 1 , wherein the NAND flash memory device is further to:
couple the second plurality of bitlines to the fixed bias voltage in response to a second read command;
apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and
sense, via the first plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the first plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

3. The apparatus of claim 1 , wherein the first plurality of bitlines coupled to the fixed bias voltage comprises every other bitline of a set of bitlines.

4. The apparatus of claim 1 , further comprising a storage device controller to communicate the first read command to the memory device controller, and wherein the memory device controller is to determine which bitlines to couple to the fixed bias voltage based on at least one address included in the first read command.

5. The apparatus of claim 1 , wherein the first read command is received from a host computing device coupled to the NAND flash memory device.

6. The apparatus of claim 1 , wherein the first read command is a program verify command performed during a program operation to verify whether a plurality of NAND flash memory cells are programmed to appropriate voltage levels.

7. The apparatus of claim 1 , wherein the first read command is performed during a calibration procedure that is to determine one or more read voltage levels to be applied to the wordline in response to receiving a read command from a host computing device.

8. The apparatus of claim 1 , wherein the sensing of the second plurality of bitlines is performed at predefined time intervals during a ramping up by the ramped architecture of a read voltage of the wordline from an initial voltage to a final voltage in a generally linear fashion.

9. The apparatus of claim 1 , wherein the sensing of the second plurality of bitlines is performed after a read voltage applied to the wordline is stepped up and held constant for a period of time by the stepped architecture.

10. A method comprising:
programming data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines;
coupling the first plurality of bitlines to a fixed bias voltage in response to a first read command;
selecting one of a stepped architecture and a ramped architecture to apply one or more read voltages to the wordline in response to the first read command, the selection based on a number of sense operations to be performed during performance of the first read command;
applying the one or more read voltages to the wordline coupled to the plurality of NAND flash memory cells via the selected stepped or ramped architecture; and
sensing, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

11. The method of claim 10 , further comprising:
coupling the second plurality of bitlines to the fixed bias voltage in response to a second read command;
applying a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and
sensing, via the first plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the first plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

12. The method of claim 10 , wherein the first plurality of bitlines coupled to the fixed bias voltage comprises every other bitline of a set of bitlines.

13. The method of claim 10 , wherein the first read command is received from a host computing device coupled to a storage device.

14. The method of claim 10 , wherein the first read command is performed during a calibration procedure that is to determine one or more read voltage levels to be applied to the wordline in response to receiving a read command from a host computing device.

15. A system comprising:
a host computing device comprising a processor, the host computing device to send read commands to a storage device; and
a storage device comprising at least one NAND flash memory array;
wherein the storage device is to:
program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines;
couple the first plurality of bitlines to a fixed bias voltage in response to a first read command;
select one of a stepped architecture and a ramped architecture of the storage device to apply one or more read voltages to the wordline in response to the first read command, the selection performed by the storage device based on a number of sense operations to be performed during performance of the first read command;
apply the one or more read voltages to the wordline coupled to the plurality of NAND flash memory cells via the selected stepped or ramped architecture; and
sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

16. The system of claim 15 , wherein the storage device is further to:
couple the second plurality of bitlines to the fixed bias voltage in response to a second read command;
apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and
sense, via the first plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the first plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

17. The system of claim 15 , wherein the first plurality of bitlines coup

Assignees

• Intel Corp

Inventors

• Helm Mark
• Yip Aaron

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title