FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-11081583-B2 · Aug 3, 2021 · US
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Harley Eric C patents
Harley Eric C is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Harley Eric C |
| Total patents | 27 |
| First publication | Jan 15, 2015 |
| Latest publication | Aug 3, 2021 |
Notable patents
Publications ranked by popularity score, then publication date.
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-10615279-B2 · Apr 7, 2020 · US
Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-2020066908-A1 · Feb 27, 2020 · US
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-10243077-B2 · Mar 26, 2019 · US
Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-2018097113-A1 · Apr 5, 2018 · US
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-9917190-B2 · Mar 13, 2018 · US
Self-limiting selective epitaxy process for preventing merger of semiconductor fins
US-9752251-B2 · Sep 5, 2017 · US
FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
US-9577100-B2 · Feb 21, 2017 · US
Method for embedded diamond-shaped stress element
US-9412843-B2 · Aug 9, 2016 · US
Method of inspecting a semiconductor substrate
US-9390884-B2 · Jul 12, 2016 · US
Recent patents
Latest publications not already listed above.
Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-2016197186-A1 · Jul 7, 2016 · US
finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-9312364-B2 · Apr 12, 2016 · US
Partial fin on oxide for improved electrical isolation of raised active regions
US-2016079397-A1 · Mar 17, 2016 · US
Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-2016035878-A1 · Feb 4, 2016 · US
FINFET structures with fins recessed beneath the gate
US-9246003-B2 · Jan 26, 2016 · US
Graphene transistor with a sublithographic channel width
US-9236477-B2 · Jan 12, 2016 · US
Partial FIN on oxide for improved electrical isolation of raised active regions
US-9219114-B2 · Dec 22, 2015 · US
Finfet and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
US-2015364603-A1 · Dec 17, 2015 · US
Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth
US-2015349093-A1 · Dec 3, 2015 · US
Method for embedded diamond-shaped stress element
US-2015340465-A1 · Nov 26, 2015 · US
Semiconductor inspection system including reference image generator
US-2015325406-A1 · Nov 12, 2015 · US
Single-crystal source-drain merged by polycrystalline material
US-2015270332-A1 · Sep 24, 2015 · US
Single crystal source-drain merged by polycrystalline material
US-9123826-B1 · Sep 1, 2015 · US
Graphene transistor with a sublithographic channel width
US-2015236147-A1 · Aug 20, 2015 · US
Finfet structures with fins recessed beneath the gate
US-2015137193-A1 · May 21, 2015 · US
Multigate finFETs with epitaxially-grown merged source/drains
US-8987093-B2 · Mar 24, 2015 · US
Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions
US-2015014773-A1 · Jan 15, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 21 |
| Globalfoundries Inc | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/024 | 21 |
| H10D30/62 | 18 |
| H01L29/66795 | 17 |
| H10D30/797 | 16 |
| H10D62/822 | 14 |