FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Patent metadata

Field	Value
Publication number	US-11081583-B2
Application number	US-201916665338-A
Country	US
Kind code	B2
Filing date	Oct 28, 2019
Priority date	May 27, 2014
Publication date	Aug 3, 2021
Grant date	Aug 3, 2021

Abstract

A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a gate structure present on a channel region portion of a plurality of fin structures, the gate structure formed over a substrate;
a flowable dielectric material present filling a space between adjacent fin structures in the plurality of fin structures;
a dielectric material encompassing the plurality of fins structures; and
a first epitaxial merge structure formed over a first set of the plurality of fin structures and a second epitaxial merge structure formed over a second set of the plurality of fin structures, wherein the first and second epitaxial merge structures are separate and distinct from each other and each extend over portions of the flowable dielectric material, and wherein the first epitaxial merge structure includes a buffer layer with semi-circular protrusions extending laterally from an upper portion thereof,
wherein the dielectric material prevents direct contact between the plurality of fins and the flowable dielectric material, and
wherein the dielectric material prevents directs contact between the flowable dielectric material and the substrate.

2. The semiconductor device of claim 1 , wherein the flowable dielectric material includes an oxide.

3. The semiconductor device of claim 1 , wherein the gate structure includes at least one gate dielectric and at least one gate conductor.

4. The semiconductor device of claim 1 , wherein the first and second epitaxial merge structures are composed of silicon germanium, silicon doped with carbon, or a combination thereof.

5. The semiconductor device of claim 1 , wherein the upper surface of the plurality of the fin structures is recessed.

6. The semiconductor device of claim 1 , wherein a cap layer portion is disposed over the first epitaxial merge structure and in direct contact with upper surfaces of the buffer layer.

7. The semiconductor device of claim 1 , wherein the flowable dielectric material includes a spin on glass, a flowable chemical vapor deposition (FCVD) or a combination thereof.

8. The semiconductor device of claim 1 , further comprising a gate sidewall spacer on sidewalls of the gate structure formed after the flowable dielectric.

9. The semiconductor device of claim 1 , wherein the first epitaxial merge structure includes silicon and germanium semiconductor material associated with p-type fin field effect transistors (FinFETs).

10. The semiconductor device of claim 1 , wherein the second epitaxial merge structure includes silicon and carbon semiconductor material associate with n-type fin field effect transistors (FinFETs).

Assignees

• IBM

Inventors

• Harley Eric C
• Holt Judson R
• Ke Yue
• Krishnan Rishikesh
• Tabakman Keith H
• Utomo Henry K

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title