FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Patent metadata

Field	Value
Publication number	US-9577100-B2
Application number	US-201414305543-A
Country	US
Kind code	B2
Filing date	Jun 16, 2014
Priority date	Jun 16, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate structure present on at least one suspended channel structure, wherein at least one gate dielectric layer is present surrounding, and in contact with, the at least one suspended channel structure and at least one gate conductor is present on the at least one gate dielectric layer; and
source and drain structures comprised of a strain inducing material, wherein the source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a semiconductor cladding layer formed on sidewalls of the source and drain ends of the suspended channel structure, wherein a lattice dimension of the strain inducing material is different from a lattice dimension of the semiconductor cladding layer.

2. The semiconductor device of claim 1 , wherein the at least one suspended channel structure includes multiple suspended channel structures.

3. The semiconductor device of claim 1 , wherein the at least one suspended channel structure has an oblong geometry.

4. The semiconductor device of claim 1 , w herein the suspended channel structure is composed of intrinsic silicon, the source and drain structures are composed of silicon germanium doped with an n-type or p-type dopant, and the semiconductor cladding layer is composed of intrinsic silicon.

5. The semiconductor device of claim 1 , wherein the semiconductor cladding layer includes a crystalline crystal structure oriented to a crystal arrangement of an underlying semiconductor material, and wherein the semiconductor cladding layer conformally contacts the sidewalls of the source and drain ends of the suspended channel structure in addition to an upper surface of the underlying semiconductor material.

6. The semiconductor device of claim 1 , wherein the lattice dimension of the strain inducing material is less than the lattice dimension of the semiconductor cladding layer, such that the source and drain structures induce a tensile strain on the suspended channel structure.

7. The semiconductor device of claim 1 , wherein the lattice dimension of the strain inducing material is greater than the lattice dimension of the semiconductor cladding layer, such that the source and drain structures induce a compressive strain on the suspended channel structure.

8. A semiconductor device comprising:
a gate structure present on at least one nanowire channel structure, wherein at least one gate dielectric layer is present surrounding, and in contact with, the at least one nanowire channel, and at least one gate conductor is present on the at least one gate dielectric layer; and
epitaxial source and drain structures comprised of a strain inducing material, the epitaxial source and drain structures in contact with the source and drain region ends of the plurality of the suspended nanowire structures through a semiconductor cladding layer formed on sidewalls of the source and drain region ends of each of the plurality of suspended nanowire structures, wherein a lattice dimension of the strain inducing material is different from a lattice dimension of the semiconductor cladding layer, such that the epitaxial source and drain structures induce one of a compressive strain or a tensile strain on the at least one nanowire channel through the silicon cladding region.

9. The semiconductor device of claim 8 , wherein the at least one suspended nanowire structure includes multiple suspended channel structures.

10. The semiconductor device of claim 8 , wherein the at least one suspended nanowire has an oblong geometry.

11. The semiconductor device of claim 8 , wherein the silicon cladding region includes a crystalline crystal structure oriented to a crystal arrangement of an underlying semiconductor material, and wherein the semiconductor cladding layer conformally contacts the sidewalls of the source and drain ends of the plurality of the suspended nanowire structures in addition to an upper surface of the underlying semiconductor material.

12. The semiconductor device of claim 8 , wherein the lattice dimension of the strain inducing material is less than the lattice dimension of the silicon cladding region, such that the epitaxial source and drain structures induce the tensile strain on the plurality of the at least one nanowire channel.

13. The semiconductor device of claim 8 , wherein the lattice dimension of the strain inducing material is greater than the lattice dimension of the silicon cladding region, such that the epitaxial source and drain structures induce the compressive strain on the at least one nanowire channel.

Assignees

• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Chudzik Michael P
• Harley Eric C
• Holt Judson R
• Ke Yue
• Krishnan Rishikesh
• Rim Kern
• Utomo Henry K

Classifications

• H10P50/642

  Chemical etching · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/6681

  Electricity · mapped topic

• H01L29/7851 Primary

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic