Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth

Patent metadata

Field	Value
Publication number	US-2016197186-A1
Application number	US-201615070515-A
Country	US
Kind code	A1
Filing date	Mar 15, 2016
Priority date	May 27, 2014
Publication date	Jul 7, 2016
Grant date	—

Abstract

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

First claim

What is claimed is:

1 . A method of forming a semiconductor device comprising:
forming a gate structure on a channel region of a plurality of fin structures; forming a flowable dielectric material on a source region portion and a drain region portion of the plurality of fin structures, wherein the flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between said adjacent fin structures; exposing an upper surface of the source region portion and the drain region portion of the plurality of fin structures; and forming an epitaxial semiconductor material on the upper surface of the source region portion and the drain region portion of the plurality of fin structures.

2 . The method of claim 1 , wherein the forming of the gate structure on the channel region portion of the plurality of fin structures comprises:
forming a sacrificial gate structure on the channel region of the fin structures prior to forming the epitaxial semiconductor material; removing the sacrificial gate structure after forming the epitaxial semiconductor material; and forming a functional gate structure on the channel region portion for the plurality of fin structures in the space formed by said removing the sacrificial gate structure.

3 . The method of claim 1 , wherein prior to said forming the flowable dielectric material, a dielectric layer is formed on the source region portion and the drain region portion of the plurality of fin structures.

4 . The method of claim 1 , wherein the flowable dielectric material is an oxide.

5 . The method of claim 1 , wherein the flowable dielectric material is deposited using spin on glass deposition, flowable chemical vapor deposition (FCVD) or a combination thereof.

6 . The method of claim 1 further comprising forming a gate sidewall spacer on sidewalls of the gate structure after forming the flowable dielectric.

7 . The method of claim 3 , wherein said exposing the upper surface of the source region portion and the drain region portion of the plurality of fin structures comprises removing the dielectric layer from the upper surface of the source region portion and the drain region portion of the plurality fin structures.

8 . The method of claim 1 , wherein the forming of the epitaxial semiconductor material on the upper surface of the source region portion and the drain region portion of the plurality of fin structures comprises:
forming a silicon and germanium including semiconductor material on the source region portion and the drain region portion of the plurality of fin structures that provide p-type FinFETs; and forming a silicon and carbon including semiconductor material on the source region portion and the drain region portion of the plurality of fin structures that provide n-type FinFETs.

9 . The method of claim 1 , wherein epitaxial semiconductor material is an epitaxial semiconductor merge source and drain region structure that extends into contact with adjacent fin structures in the plurality of fin structures.

10 . A method of forming a semiconductor device comprising:
forming a gate structure on a channel region of a plurality of fin structures; forming a dielectric layer on a source region portion and a drain region portion of the plurality of fin structures; depositing a flowable dielectric material on the source region portion and the drain region portion of the plurality of fin structures over the dielectric layer, wherein the flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between said adjacent fin structures; exposing an upper surface of the source region portion and the drain region portion of the fin structures by etching the dielectric layer; recessing the upper surface of the plurality of fin structures; and forming an epitaxial semiconductor material on the upper surface of the source region portion and the drain region portion of the plurality of fin structures that has been recessed.

11 . The method of claim 10 , wherein the flowable dielectric material is deposited using spin on glass deposition, flowable chemical vapor deposition (FCVD) or a combination thereof.

12 . The method of claim 10 further comprising forming a gate sidewall spacer on sidewalls of the gate structure after forming the flowable dielectric material.

13 . The method of claim 10 , wherein the forming of the epitaxial semiconductor material on the upper surface of the source region portion and the drain region portion of the plurality of fin structures comprises:
forming a silicon and germanium including semiconductor material on the source region portion and the drain region portion of the plurality of fin structures that provide p-type FinFETs; and forming a silicon and carbon including semiconductor material on the source region portion and the drain region portion of the plurality of fin structures that provide n-type FinFETS.

14 . The method of claim 10 , wherein epitaxial semiconductor material is an epitaxial semiconductor merge source and drain region structure that extends into contact with adjacent fin structures in the plurality of fin structures.

15 . A semiconductor device comprising:
a gate structure present on a channel region portion of a plurality of fin structures; a flowable dielectric material present filling the space between adjacent fin structures in the plurality of fin structures; and epitaxial source and drain merge structures present on an exposed upper surface of the fin structures, wherein the epitaxial source and drain merge structures extend over the flowable dielectric material that is present filling the space between adjacent fin structures.

16 . The semiconductor device of claim 15 , wherein the flowable dielectric material is an oxide.

17 . The semiconductor device of claim 15 , wherein the gate structure includes at least one gate dielectric and at least one gate conductor.

18 . The semiconductor device of claim 15 , wherein epitaxial source and drain merge structures are composed of silicon germanium, silicon doped with carbon, or a combination thereof.

19 . The semiconductor device of claim 15 , wherein the upper surface of the plurality of the fin structures that the epitaxial source and drain merge structures are present on is recessed.

20 . The semiconductor device of claim 19 , wherein the epitaxial source and drain merge structures comprise a buffer layer portion, a main portion, and a cap layer portion.

Assignees

• IBM

Inventors

• Harley Eric C
• Holt Judson R
• Ke Yue
• Krishnan Rishikesh
• Tabakman Keith H
• Utomo Henry K

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title