Method for embedded diamond-shaped stress element

Patent metadata

Field	Value
Publication number	US-9412843-B2
Application number	US-201414285967-A
Country	US
Kind code	B2
Filing date	May 23, 2014
Priority date	May 23, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A method of manufacturing a semiconductor device with an embedded layer, by anisotropically etching a substrate adjacent to an already formed gate structure. A dummy layer is deposited in the previously etched region, and a second spacer is formed next to the first spacer. The dummy layer is removed, and a second anisotropic etch is performed. A semiconductor substrate is then epitaxially grown in the etched out region to form the embedded layer.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
performing a first etch, wherein the first etch comprises anisotropically etching a region of a semiconductor substrate adjacent to a gate to form a recessed region in the semiconductor substrate, wherein the gate comprises a gate stack, and a pair of first spacers sandwiching the gate stack;
forming a dummy layer in the recessed region of the semiconductor substrate;
forming a pair of second spacers adjacent to the pair of first spacer, wherein a bottom surface of the pair of second spacers is defined by a top surface of the dummy layer;
removing all of the dummy layer;
performing a second etch, wherein the second etch comprises anisotropically etching the semiconductor substrate such that a recessed source/drain region extends underneath the dielectric spacers; and
epitaxially growing a source/drain region in the recessed source/drain region of the semiconductor substrate.

2. The method of claim 1 , wherein the first etch comprises a anisotropic etch along the vertical plane of the substrate.

3. The method of claim 2 , wherein the vertical anisotropic etch comprises wet silicon etching or plasma etching.

4. The method of claim 1 , wherein the second etch comprises an anisotropic etch along the <111> plane of the substrate.

5. The method of claim 4 , wherein the second etch comprises a gaseous etch process.

6. The method of claim 1 , wherein the material of the source/drain region is a material with a larger lattice constant than silicon.

7. The method of claim 6 , wherein the material of the source/drain region is silicon germanium.

8. The method of claim 1 , wherein the material of the source/drain region is a material with a smaller lattice constant than silicon.

9. The method of claim 6 , wherein the material of the source/drain region is carbon doped silicon.

10. The method of claim 1 , wherein the recessed region is a diamond shaped recess or a sigma recess.

11. The method of claim 1 , wherein the dummy layer material comprises germanium.

12. The method of claim 1 , wherein forming the dummy later further comprises completely filling the recessed region.

13. The method of claim 1 , wherein a vertical surface of the recessed region adjacent to the gate is substantially coplanar to the outer edge of the first spacer pair.

14. A method of forming a semiconductor structure, the method comprising:
performing a first etch, wherein the first etch comprises anisotropically etching a region of a semiconductor substrate adjacent to a gate to form a recessed region in the semiconductor substrate, wherein the gate comprises a gate stack, and a pair of first spacers sandwiching the gate stack, wherein the first etch comprises an anisotropic etch along a vertical plane of the substrate;
forming a dummy layer in the recessed region of the semiconductor substrate;
forming a pair of second spacers adjacent to the pair of first spacer, wherein a bottom surface of the pair of second spacers is defined by a top surface of the dummy layer;
removing all of the dummy layer;
performing a second etch to form a recessed source/drain region, wherein the second etch comprises an anisotropic etch along the <111> plane of the substrate; and
epitaxially growing a source/drain region in the recessed source/drain region of the semiconductor substrate.

15. The method of claim 14 , wherein the first etch comprises wet silicon etching or plasma etching.

16. The method of claim 14 , wherein the second etch comprises a gaseous etch process.

17. The method of claim 14 , wherein the material of the source/drain region is a material with a larger lattice constant than silicon.

18. The method of claim 17 , wherein the material of the source/drain region is silicon germanium.

19. The method of claim 14 , wherein the material of the source/drain region is a material with a smaller lattice constant than silicon.

20. The method of claim 14 , wherein the material of the source/drain region is carbon doped silicon.

Assignees

• IBM

Inventors

• Harley Eric C
• Holt Judson R
• Wallner Jin Z
• Wallner Thomas A

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title