FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Patent metadata

Field	Value
Publication number	US-10243077-B2
Application number	US-201715820809-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	May 27, 2014
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

First claim

What is claimed is:

1. A semiconductor device comprising:
a conformal dielectric layer on a sidewall of a plurality of fin structures, wherein the conformal dielectric layer comprises recessed vertically orientated portions along sidewall surfaces of source and drain region portions of the plurality of fin structures;
a flowable dielectric material present filling a space between said adjacent fin structures in the plurality of fin structures, wherein an upper surface of the recessed vertically orientated portions of the conformal dielectric layer are also recessed relative to an upper surface of the flowable dielectric material to provide a recess between the fin structures and the flowable dielectric material; and
epitaxial source and drain merge structures in direct contact with a majority of an upper surface of the source and drain region portions of fin structures and in direct contact with upper sidewall surfaces on the source and drain region portions of the fin structures that are atop the recessed vertically oriented portions of the conformal dielectric layer that are present on the source and drain region portions of the fin structures, wherein the epitaxial semiconductor material of the epitaxial source and drain merge structures fills the recess between the fin structures and the flowable dielectric material.

2. The semiconductor device of claim 1 , wherein the epitaxial source and drain merge structures extend over the flowable dielectric material that is present filling the space between the adjacent fin structures.

3. The semiconductor device of claim 1 , wherein an epitaxial semiconductor material of the epitaxial source and drain merge structures fills the recess between the fin structures and the flowable dielectric material and is present on the upper surface of the conformal dielectric layer that is recessed relative to the upper surface of the flowable dielectric material.

4. The semiconductor device of claim 3 , wherein the epitaxial source and drain merge structures comprise a buffer layer portion, a main portion, and a cap layer portion.

5. The semiconductor device of claim 1 , wherein the flowable dielectric material is an oxide.

6. The semiconductor device of claim 1 , further comprising a gate structure on a channel region portion of the fin structures.

7. The semiconductor device of claim 6 , wherein the gate structure includes at least one gate dielectric and at least one gate conductor.

8. The semiconductor device of claim 1 , wherein the epitaxial source and drain merge structures are composed of a semiconductor material selected from the group consisting of silicon germanium, silicon doped with carbon, and combinations thereof.

9. The semiconductor device of claim 1 , wherein the upper surface of the plurality of the fin structures that the epitaxial source and drain merge structures are present on is recessed.

10. The semiconductor device of claim 1 , wherein the epitaxial source and drain merge structures are in direct contact with an upper surface of the recessed vertically oriented portions of the conformal dielectric layer.

Assignees

• IBM

Inventors

• Harley Eric C
• Holt Judson R
• Ke Yue
• Krishnan Rishikesh
• Tabakman Keith H
• Utomo Henry K

Classifications

• H01L29/0847

  Electricity · mapped topic

• H01L21/823878

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic