FINFET structures with fins recessed beneath the gate

Patent metadata

Field	Value
Publication number	US-9246003-B2
Application number	US-201314083517-A
Country	US
Kind code	B2
Filing date	Nov 19, 2013
Priority date	Nov 19, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

First claim

The invention claimed is:

1. A method of forming a semiconductor structure, the method comprising:
forming a gate above a portion of a semiconductor fin on a substrate;
forming a spacer on a sidewall of the gate;
removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin;
etching the sidewall of the fin to form an angled recess region beneath the spacer;
growing a first epitaxial semiconductor region on the substrate, the first epitaxial semiconductor region filling the angled recess region and contacting the fin;
removing portions of the first epitaxial semiconductor region outside of the angled recess region; and
growing a second epitaxial semiconductor region on the substrate, the second epitaxial semiconductor region contacting a portion of the first epitaxial semiconductor region in the angled recess region.

2. The method of claim 1 , wherein the first epitaxial semiconductor region has the same material composition but a lower dopant concentration than the second epitaxial semiconductor region.

3. The method of claim 1 , wherein the angled recess region is v-shaped.

4. The method of claim 1 , wherein the angled recess region is sigma-shaped.

5. The method of claim 1 , wherein the first semiconductor region comprises a stressor material.

6. The method of claim 5 , wherein the first semiconductor region comprises silicon germanium or carbon-doped silicon.

7. A method of forming a semiconductor structure, the method comprising:
forming a gate above a first portion of the semiconductor fin on a substrate, wherein a second portion of the semiconductor fin is not covered by the gate;
forming a spacer on a sidewall of the gate;
removing the second portion of the semiconductor fin;
forming a stressor region in an end of the first portion of the semiconductor fin, wherein the stressor region comprises a first epitaxial semiconductor material having an angled shape with the tallest portion of the stressor region adjacent to the end of the semiconductor fin, wherein an outer sidewall surface of the stressor region does not extend beyond an outer sidewall surface of the spacer;
forming an epitaxial semiconductor region comprising a second epitaxial semiconductor material adjacent to the stressor region, said epitaxial semiconductor region has a sidewall surface directly contacting the outer sidewall surface of the stressor region and a bottommost surface contacting a surface of the substrate.

8. The method of claim 7 , wherein the stressor region is v-shaped.

9. The method of claim 7 , wherein the stressor region is sigma-shaped.

10. The method of claim 7 , wherein the first epitaxial semiconductor material of the stressor region has the same material composition but a lower dopant concentration than the second epitaxial semiconductor material of the epitaxial semiconductor region.

11. The method of claim 7 , wherein the stressor region comprises silicon-germanium or carbon-doped silicon.

12. A semiconductor structure comprising:
a semiconductor fin on a substrate;
a gate over the semiconductor fin;
a spacer on a sidewall of the gate;
an angled recess region in an end of the semiconductor fin beneath the spacer;
a first semiconductor region filling the angled recess region, the first semiconductor region is located beneath the spacer and has an outer sidewall surface that is vertically aligned to an outer sidewall surface of the spacer; and
a second semiconductor region having a sidewall surface directly contacting the outer sidewall surface of the first semiconductor region and vertically aligned to the outer sidewall surface of the spacer and a bottommost surface contacting a surface of the substrate.

13. The structure of claim 12 , wherein the angled recess region is v-shaped.

14. The structure of claim 12 , wherein the angled recess region is sigma-shaped.

15. The structure of claim 12 , wherein the first semiconductor region applies stress to the semiconductor fin.

16. The structure of claim 12 , wherein the first semiconductor region comprises a stressor material.

17. The semiconductor structure of claim 12 , wherein the first semiconductor region contacts the substrate.

18. The semiconductor structure of claim 12 , wherein the first semiconductor region has the same material composition but a lower dopant concentration than the second semiconductor region.

Assignees

• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Harley Eric C
• Ke Yue
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/791 Primary

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title