Self-limiting selective epitaxy process for preventing merger of semiconductor fins

Patent metadata

Field	Value
Publication number	US-9752251-B2
Application number	US-201313862759-A
Country	US
Kind code	B2
Filing date	Apr 15, 2013
Priority date	Apr 15, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A self-limiting selective epitaxy process can be employed on a plurality of semiconductor fins such that the sizes of raised active semiconductor regions formed by the selective epitaxy process are limited to dimensions determined by the sizes of the semiconductor fins. Specifically, the self-limiting selective epitaxy process limits growth of the semiconductor material along directions that are perpendicular to crystallographic facets formed during the selective epitaxy process. Once the crystallographic facets become adjoined to one another or to a dielectric surface, growth of the semiconductor material terminates, thereby preventing merger among epitaxially deposited semiconductor materials.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
providing at least one semiconductor fin including a first single crystalline semiconductor material on a substrate;
growing a plurality of faceted semiconductor material portions including a second single crystalline semiconductor material on semiconductor surfaces of said at least one semiconductor fin by flowing at least one reactant precursor for said second single crystalline semiconductor material and an etchant in a selective epitaxy process performed in a process chamber for a duration of time, wherein a flow rate of said at least one reactant precursor and a flow rate of said etchant are selected to provide a set of crystallographically equivalent orientations in which a net deposition rate of said second single crystalline semiconductor material is either zero or negative thereby growth of said plurality of faceted semiconductor material portions stops when all of physically exposed surfaces of said plurality of faceted semiconductor material portions become faceted surfaces having crystallographically equivalent orientations within said set of crystallographically equivalent orientations;
forming a contact-level dielectric material surrounding each semiconductor fin and in direct contact with a bottom portion of said faceted semiconductor material portions, wherein said contact-level dielectric material has contact openings;
forming a metal semiconductor alloy portion within said contact openings and directly on an upper surface of said faceted semiconductor material portions, wherein a bottom surface and a top surface of said metal semiconductor alloy portion are faceted; and
forming a contact via structure directly on said faceted upper surface of metal alloy portion, wherein outermost vertical sidewalls of said metal semiconductor alloy portion are vertically aligned with outermost vertical sidewalls of said contact via structure.

2. The method of claim 1 , wherein all of said physically exposed surfaces of said plurality of faceted semiconductor material portions become adjoined to one another or to one or more dielectric surfaces.

3. The method of claim 1 , wherein said faceted surfaces having said crystallographically equivalent orientations contact one another or one or more dielectric surfaces.

4. The method of claim 1 , wherein said substrate comprises an insulator layer, and said at least one semiconductor fin is formed directly on a top surface of said insulator layer.

5. The method of claim 4 , wherein said faceted surfaces are not parallel to, or perpendicular to, said top surface of said insulator layer.

6. The method of claim 1 , wherein said crystallographically equivalent orientations are {111} orientations.

7. The method of claim 1 , wherein each of said at least one semiconductor fin includes a pair of vertical sidewalls that extend along a lengthwise direction, and said plurality of faceted semiconductor material portions are deposited on all surfaces of said at least one pair of vertical sidewalls.

8. The method of claim 1 , wherein each of said faceted surfaces becomes adjoined to at least another of said faceted surfaces no later than when said growth of said plurality of faceted semiconductor material portions stops.

9. The method of claim 1 , wherein said plurality of faceted semiconductor material portions does not change in size after said growth of said plurality of faceted semiconductor material portions stops.

10. The method of claim 1 , wherein said plurality of faceted semiconductor material portions decreases in size after said growth of said plurality of faceted semiconductor material portions stops.

11. The method of claim 1 , wherein said second single crystalline semiconductor material is a single crystalline silicon-germanium alloy.

12. The method of claim 11 , wherein an atomic concentration of germanium in said second single crystalline semiconductor material is in a range from 10% to 50%.

13. The method of claim 11 , wherein said first single crystalline semiconductor material includes silicon at an atomic concentration of at least 90%.

14. The method of claim 13 , wherein said first single crystalline semiconductor material consists of silicon or consists of silicon and at least one electrical dopant.

15. The method of claim 1 , wherein said at least one reactant precursor comprises at least one silicon-containing precursor and at least one germanium-containing precursor.

16. The method of claim 15 , wherein said at least one silicon-containing precursor comprises at least one of SiH 4 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , and Si 2 H 6 .

17. The method of claim 15 , wherein said at least one germanium-containing precursor comprises at least one of GeH 4 and Ge 2 H 6 .

18. The method of claim 1 , wherein said etchant comprises HCl.

19. The method of claim 1 , wherein a molar ratio of said at least one reactant precursor to said etchant is in a range from 4:1 to 1:4 in said process chamber during said selective epitaxy process.

20. The method of claim 1 , wherein a partial pressure of said etchant is in a range from 1 mTorr to 10 Torr, and a partial pressure of all of said at least one reactant precursor is in a range from 1 mTorr to 5 Torr.

21. The method of claim 1 , wherein said at least one reactant precursor does not nucleate on any dielectric surface during said selective epitaxy process.

22. The method of claim 1 , wherein said at least one semiconductor fin is a plurality of semiconductor fins, and a subset of said plurality of faceted semiconductor material portions that are formed directly on one of said plurality of semiconductor fins does not contact any other subset of said plurality of faceted semiconductor material portions that are formed directly on any other of said plurality of semiconductor fins.

23. The method of claim 1 , further comprising interdiffusing semiconductor materials across said at least one semiconductor fin and said plurality of faceted semiconductor material portions by an anneal at an elevated temperature.

24. The method of claim 1 , further comprising forming a gate stack structure across said at least one semiconductor fin prior to performing said selective epitaxy process, wherein said gate stack structure includes a stack of a gate dielectric and a gate electrode.

25. The method of claim 24 , further comprising forming a source region and a drain region within end portions of each contiguous set of said at least one semiconductor fin and said plurality of faceted semiconductor material portions, wherein said source region and said drain region are laterally spaced from each other by a body region underlying said gate stack structure.

Assignees

• IBM

Inventors

• Chan Kevin K
• Harley Eric C
• Ke Yue
• Levesque Annie

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title