Programmable event driven yield mechanism which may activate other threads
US-10877910-B2 · Dec 29, 2020 · US
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Hammarlund Per patents
Hammarlund Per is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Hammarlund Per |
| Total patents | 21 |
| First publication | Mar 12, 2015 |
| Latest publication | Dec 29, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Programmable event driven yield mechanism which may activate other threads
US-10459858-B2 · Oct 29, 2019 · US
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US-10452403-B2 · Oct 22, 2019 · US
Synchronization of interrupt processing to reduce power consumption
US-10089263-B2 · Oct 2, 2018 · US
Mechanism for instruction set based thread execution of a plurality of instruction sequencers
US-9990206-B2 · Jun 5, 2018 · US
Programmable event driven yield mechanism which may activate other threads
US-9910796-B2 · Mar 6, 2018 · US
Hardware-assisted virtualization for implementing secure video output path
US-9785576-B2 · Oct 10, 2017 · US
Compare and exchange operation using sleep-wakeup mechanism
US-9733937-B2 · Aug 15, 2017 · US
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US-9720697-B2 · Aug 1, 2017 · US
Synchronization of interrupt processing to reduce power consumption
US-2017161096-A1 · Jun 8, 2017 · US
Recent patents
Latest publications not already listed above.
Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode
US-9600283-B2 · Mar 21, 2017 · US
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
US-9588771-B2 · Mar 7, 2017 · US
Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US-2017010895-A1 · Jan 12, 2017 · US
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
US-9459874-B2 · Oct 4, 2016 · US
METHOD AND APPARATUS FOR POWER OPTIMIZED IoT COMMUNICATION
US-2016095060-A1 · Mar 31, 2016 · US
Methods And Apparatuses For Reducing Power Consumption Of Processor Switch Operations
US-2016004533-A1 · Jan 7, 2016 · US
Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode
US-9164764-B2 · Oct 20, 2015 · US
Instruction for enabling a processor wait state
US-9032232-B2 · May 12, 2015 · US
Instruction for enabling a processor wait state
US-8990597-B2 · Mar 24, 2015 · US
Inter-processor interrupts
US-8984199-B2 · Mar 17, 2015 · US
Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource
US-2015070368-A1 · Mar 12, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 21 |
| Hammarlund Per | 4 |
| Wang Hong | 3 |
| Loh Thiam Wah | 2 |
| Chinya Gautham N | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3009 | 9 |
| Y02D10/00 | 8 |
| G06F9/30145 | 8 |
| G06F9/30043 | 7 |
| G06F9/4843 | 7 |