Programmable event driven yield mechanism which may activate other threads

Patent metadata

Field	Value
Publication number	US-9910796-B2
Application number	US-201313844343-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Feb 19, 2003
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

First claim

What is claimed is:

1. An apparatus comprising:
execution resources to execute a plurality of instructions;
a monitor to detect a low progress indicating a condition of said execution resources, said monitor to selectively disrupt processing of at least one program by transferring to a handler in response to detecting said low progress indicating condition, wherein the monitor logic comprises event storage logic to indicate when one of a plurality of events occur, the low progress indicating condition to include a combination of the plurality of events, wherein the event storage logic to include a plurality of event counters, each of the plurality of event counters to hold a count value corresponding to a number of events of the plurality of events that have occurred, wherein the low progress indicating condition occurs when a certain value of the count value has occurred;
a virtual thread selector to select a virtual thread from a plurality of threads and swap context information for a selected virtual thread in response to the monitor logic detecting the low progress indicating condition during the execution logic executing the program; and
a processor thread selector to select between the selected virtual thread and another thread.

2. The apparatus of claim 1 , wherein a physical thread context storage to maintain a plurality of thread contexts usable by the execution resources and wherein said apparatus caches virtual thread context data in one of a set consisting of a cache location, a register location, or other storage location.

3. The apparatus of claim 1 , wherein context information is to be cached for a plurality of virtual threads, wherein context information for a selected one of the plurality of virtual threads is switched to said physical thread context storage before active execution of said selected one of the plurality of k virtual threads.

4. The apparatus of claim 3 , wherein a set of context data for one of said plurality of virtual threads is to be cached in a storage location, wherein context information for a selected one of the plurality of k virtual threads must be switched to said physical thread context storage before active execution of said selected one of the plurality of virtual threads.

5. The apparatus of claim 1 , wherein the monitor logic further comprises mask logic corresponding to the event storage logic to be updatable to indicate the combination of the plurality of events to occur from the event storage logic to define the low progress indicating condition.

6. The apparatus of claim 3 , wherein said monitor logic is also capable of being reprogrammed by the at least one of said plurality of virtual threads to be switched into said physical thread context storage after the at least one of said plurality of virtual threads is switched into said physical thread context storage to define an additional condition, and wherein the virtual thread selector is further to cause context information for an additional virtual thread of said plurality of virtual threads to be switched into said physical context storage in response to the monitor logic detecting the additional condition.

7. The apparatus of claim 3 wherein the low progress indicating condition includes a yield type instruction is to cause a thread switch between the plurality of virtual threads.

8. A method comprising:
executing a plurality of active threads in a multithreaded processor, wherein a program associated with at least one of the active threads of the plurality of active threads defines a low progress indicating condition in hardware during executing the plurality of active threads, wherein the low progress indicating condition includes a combination of the plurality of events;
executing to a first helper thread of a plurality of helper threads in response to the hardware detecting the low progress indicating condition, wherein the low progress indicating condition occurs when a certain value of the count value has occurred in one of a plurality of event counters, each of the plurality of event counters to hold a count value corresponding to a number of events of the plurality of events that have occurred;
executing the first helper thread concurrently with at least one active thread after switching the first helper thread into the thread slot, wherein the first helper thread defines an additional trigger condition in the hardware during executing the first helper thread; and
executing a second helper thread of the plurality of helper threads in response to the hardware detecting the additional trigger condition.

9. The method of claim 8 wherein after switching the second helper thread into the another thread slot, the at least one of the active threads associated with the program, the first helper thread, and the second helper thread are concurrently executing as active threads in the plurality of thread slots, and wherein the trigger condition is selected from a group consisting of a combination of hardware events, a hardware latency event, a asynchronous yield-type instruction, and a synchronous execution-stopping instruction.

Assignees

• Intel Corp

Inventors

• Wang Hong
• Hammarlund Per
• Zou Xiang
• Shen John P
• Tian Xinmin
• Girkar Milind
• Wang Perry H
• Desai Piyush N

Classifications

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title