Programmable event driven yield mechanism which may activate other threads

Patent metadata

Field	Value
Publication number	US-10459858-B2
Application number	US-201715804939-A
Country	US
Kind code	B2
Filing date	Nov 6, 2017
Priority date	Feb 19, 2003
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

First claim

What is claimed is:

1. A system comprising:
a system memory to store program instructions and data; and
a processor comprising:
execution resources to execute the program instructions;
a monitor to detect conditions associated with the execution resources, the monitor including multiple monitor counters, at least one of the monitor counters programmable by software to count occurrences of a microarchitectural event selected from multiple events, wherein the microarchitectural event to be monitored by the monitor is programmed by setting one or more bits in a storage location, wherein the software comprises a user program, and the monitor is programmable by the user program executed at a privilege level lower than a privilege level of an operating system;
wherein the monitor is to detect a cache miss event based on the at least one monitor counter reaching a count; and
wherein, in response to detecting the cache miss event, execution of the program is to be redirected to a handler that handles an exception.

2. The system of claim 1 wherein the monitor is further configured to detect at least one low progress indicating condition other than the cache miss event.

3. The system of claim 1 wherein a low progress indicating condition is indicated by a count of microarchitectural events.

4. The system of claim 1 wherein the monitor comprises a processor performance monitor readable by a processor instruction.

5. The system of claim 1 wherein redirection to the address is to be performed by an event handler routine stored in a computer readable medium.

6. The system of claim 5 wherein the execution resources comprise multithreaded execution circuitry capable of executing a plurality of threads.

7. The system of claim 1 wherein the monitor is context sensitive.

8. The system of claim 1 wherein the cache miss event is at least partially caused by the user program.

9. The system of claim 8 wherein the privilege level comprises a ring three privilege level.

10. The system of claim 1 wherein the system memory comprises a dynamic random access memory (DRAM).

11. The system of claim 10 further comprising:
a non-volatile storage device to store the program instructions and data.

12. The system of claim 11 wherein the non-volatile storage device comprises a flash memory device.

13. The system of claim 11 wherein the non-volatile storage device comprises a magnetic storage device.

14. The system of claim 11 further comprising:
a network interface to communicatively couple the processor to a network.

Assignees

• Intel Corp

Inventors

• Wang Hong
• Hammarlund Per
• Zou Xiang
• Shen John P
• Tian Xinmin
• Girkar Milind
• Wang Perry H
• Desai Piyush N

Classifications

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F2201/86

  Event-based monitoring · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title