Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Patent metadata

Field	Value
Publication number	US-9720697-B2
Application number	US-201213608970-A
Country	US
Kind code	B2
Filing date	Sep 10, 2012
Priority date	Jun 30, 2005
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

First claim

We claim:

1. A processor for executing threads through a plurality of logical processors, comprising:
an instruction cache to store instructions; and
a plurality of processing cores;
wherein each processing core, of the plurality of processing cores, is to support simultaneous multithreading, and comprises:
an instruction fetch logic to fetch one or more of the stored instructions;
an instruction decode logic to decode the one or more of the stored instructions;
a first logic that causes the processing core to appear as multiple logical processors, and to identify from the multiple logical processors a first set of the logical processors as operating system visible and a second set of the logical processors as operating system invisible; and
a second logic to, when a thread of instructions is scheduled to be executed by the first set of the logical processors, transfer the processing of the entire thread of instructions from the first set of the logical processors to the second set of the logical processors based on a user-level instruction specifying one or more of the first or the second set of the logical processors identified by sequencer identifiers (SIDs), wherein the user-level instruction is to generate a control transfer signal from the first set of the logical processors to be received by one or more of the second set of the logical processors, and wherein the one or more of the second set of the logical processors process the thread of instructions.

2. The processor as in claim 1 further comprising:
a set of registers for storing data for multiple threads.

3. The processor as in claim 1 further comprising:
one or more processing resources which are shared among multiple threads.

4. The processor as in claim 1 , wherein the plurality of processing cores are time-multiplexed to appear as the multiple logical processors.

5. The processor as in claim 1 , wherein the multiple logical processors to execute each instruction are identified as an aggregate of addresses of the multiple logical processors.

6. The processor as in claim 1 , wherein the thread of instructions is to specify the second set of the logical processors for the thread of instructions to be transferred to.

7. The processor as in claim 1 , wherein the second set of the logical processors is to detect a signal indicating the transferring prior to executing the thread of instructions.

8. The processor as in claim 1 , wherein the second set of the logical processors is to save execution context or state associated with the first set of the logical processors prior to processing the thread of instructions.

9. The processor as in claim 1 , wherein the one or more of the stored instructions further specifies a condition or an event to cause the transfer.

10. The processor as in claim 9 , wherein the condition or the event being one or more of a trap, a page fault, and a system call.

11. A system comprising:
a memory to store an operating system; and
a processor coupled to the memory, the processor comprising:
an instruction cache to store instructions;
a plurality of processing cores;
wherein each processing core, of the plurality of processing cores, is to support simultaneous multithreading, and comprises:
an instruction fetch logic to fetch one or more of the stored instructions;
an instruction decode logic to decode the one or more of the stored instructions;
a first logic that causes the processing core to appear as multiple logical processors, and to identify from the multiple logical processors a first set of the logical processors as operating system visible and a second set of the logical processors as operating system invisible; and
a second logic to, when a thread of instructions is scheduled to be executed by the first set of the logical processors, transfer the processing of the entire thread of instructions from the first set of the logical processors to the second set of the logical processors based on a user-level instruction specifying one or more of the first or the second set of the logical processors identified by sequencer identifiers (SIDs), wherein the user-level instruction is to generate a control transfer signal from the first set of the logical processors to be received by one or more of the second set of the logical processors, and wherein the one or more of the second set of the logical processors process the thread of instructions.

12. The system of claim 11 , wherein the processor further comprises:
a set of registers for storing data for multiple threads.

13. The system of claim 11 , wherein the processor further comprises:
one or more processing resources which are shared among multiple threads.

14. The system of claim 11 , wherein the plurality of processing cores are time-multiplexed to appear as the multiple logical processors.

15. The system of claim 11 , wherein the multiple logical processors to execute each instruction are identified as an aggregate of addresses of the multiple logical processors.

16. The system of claim 11 , wherein the thread of instructions is to specify the second set of the logical processors for the thread of instructions to be transferred to.

17. The system of claim 11 , wherein the second set of the logical processors is to detect a signal indicating the transferring prior to executing the thread of instructions.

18. The system of claim 11 , wherein the second set of the logical processors is to save execution context or state associated with the first set of the logical processors prior to processing the thread of instructions.

Assignees

• Wang Hong
• Shen John
• Grochowski Ed
• Held James Paul
• Bigbee Bryant
• Kaushik Shivnandan D
• Chinya Gautham
• Zou Xiang
• Hammarlund Per
• Tian Xinmin
• Aggarwal Anil
• Rodgers Scott Dion
• Sethi Prashant
• Patel Baiju V
• Hankins Richard Andrew
• Intel Corp

Inventors

• Wang Hong
• Shen John
• Grochowski Ed
• Held James Paul
• Bigbee Bryant
• Kaushik Shivnandan D
• Chinya Gautham
• Zou Xiang
• Hammarlund Per
• Tian Xinmin
• Aggarwal Anil
• Rodgers Scott Dion
• Sethi Prashant
• Patel Baiju V
• Hankins Richard Andrew

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title