Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Patent metadata

Field	Value
Publication number	US-9990206-B2
Application number	US-201313843164-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Jun 30, 2005
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

First claim

We claim:

1. A processor, comprising:
an instruction cache to store instructions;
one or more processing resources that are shared among multiple threads;
a plurality of processing cores, wherein each processing core, of the plurality of processing cores, is to support simultaneous multithreading and comprises:
logically independent next-instruction-pointer and fetch logic to fetch one or more threads of instructions;
an instruction decode logic to decode the one or more fetched threads of instructions;
a first logic to:
cause the plurality of processing cores to appear to a user-level program as multiple logical processors by masking the asymmetry between processing cores, and identify a first set of logical processors of the multiple logical processors to execute each fetched thread without considering physical configuration of the plurality of processing cores; and

a second logic to, when a thread of instructions is scheduled to be executed on the first set of logical processors and requires use of a specific resource, transfer the processing of the entire thread of instructions from the first set of the logical processors to a second set of the logical processors responsive to receiving a control transfer instruction specifying a logical processor identifier, wherein the control transfer instruction is used to send a signal from the first set of logical processors to be received by the second set of logical processors, and wherein the logical processor specified by the control transfer instruction processes the thread of instructions.

2. The processor of claim 1 , wherein each core is a part of a sequencer.

3. The processor of claim 1 , wherein at least one thread of instructions is visible to an operating system.

4. The processor of claim 1 , wherein at least one thread of instructions is operating system sequestered.

5. The processor of claim 1 , wherein the control transfer instruction is user-level accessible.

6. The processor of claim 1 , wherein the control transfer instruction includes an opcode, an operand for a sequencer identifier for a destination logical processor, and an operand for one of a plurality of architecturally defined scenarios.

7. The processor of claim 6 , wherein the one of the plurality of architecturally defined scenario is a begin proxy scenario.

8. The processor of claim 1 , wherein the processing core to save a context of an executing thread in response to the control transfer instruction.

9. The processor of claim 8 , wherein the context is to be saved in by an execution of a context save instruction.

10. A system comprising:
a memory to store an operating system;
a processor coupled to the memory, the processor comprising:
an instruction cache to store instructions;
one or more processing resources that are shared among multiple threads;
a plurality of processing cores, wherein each processing core, of the plurality of processing cores, is to support simultaneous multithreading and comprises:
logically independent next-instruction-pointer and fetch logic to fetch one or more threads of instructions;
an instruction decode logic to decode the one or more fetched threads of instructions;
a first logic to:
cause the plurality of processing cores to appear to a user-level program as multiple logical processors by masking the asymmetry between processing cores, and
identify a first set of logical processors of the multiple logical processors to execute each fetched thread without considering physical configuration of the plurality of processing cores; and

a second logic to, when a thread of instructions is schedule to be executed on the first set of logical processors and requires use of a specific resource, transfer the processing of the entire thread of instructions from the first set of the logical processors to a second set of the logical processors responsive to receiving a control transfer instruction specifying a logical processor identifier, wherein the control transfer instruction is used to send a signal from the first set of logical processors to be received by the second set of logical processors, and wherein the logical processor specified by the control transfer instruction processes the thread of instructions.

11. The system of claim 10 , wherein each core is a part of a sequencer.

12. The system of claim 10 , wherein at least one thread of instructions is visible to the operating system.

13. The system of claim 10 , wherein at least one thread of instructions is operating system sequestered.

14. The system of claim 10 , wherein the control transfer instruction is user-level accessible.

15. The system of claim 10 , wherein the control transfer instruction includes an opcode, an operand for a sequencer identifier for a destination logical processor, and an operand for one of a plurality of architecturally defined scenarios.

16. The system of claim 15 , wherein the one of the plurality of architecturally defined scenario is a begin proxy scenario.

17. The system of claim 10 , wherein the processing core to save a context of an executing thread in response to the control transfer instruction.

18. The system of claim 17 , wherein the context is to be saved in by an execution of a context save instruction.

Assignees

• Intel Corp

Inventors

• Wang Hong
• Shen John
• Grochowski Edward
• Hankins Richard
• Chinya Gautham
• Bigbee Bryant
• Kaushik Shivnandan
• Zou Xiang Chris
• Hammarlund Per
• Rodgers Scott Dion
• Tian Xinmin
• Aggawal Anil
• Sethi Prashant
• Patel Baiju
• Held James

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F9/30174

  for non-native instruction set, e.g. Javabyte, legacy code · CPC title