Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Patent metadata

Field	Value
Publication number	US-9459874-B2
Application number	US-201414541933-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Dec 29, 2005
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a first core to perform instructions;
an accelerator to perform at least one operation on data to be received from the first core, wherein the accelerator is a heterogeneous resource with respect to the first core and comprising a sequencer having next instruction pointer logic to determine a next instruction to be executed by the accelerator, the accelerator comprising a graphics processor having a plurality of processing engines, at least some of the plurality of processing engines to be disabled for execution of a graphics function by configuration of a system including a graphics component to perform the graphics function according to a disable indicator programmed by a basic input/output system (BIOS), the at least some of the plurality of processing engines to execute a task unrelated to the graphics function responsive to a command from the first core; and
an interface logic coupled to the accelerator to enable inter-sequencer communication between the first core and the accelerator, the interface logic to receive the inter-sequencer communication and translate the inter-sequencer communication to a native instruction sequence of the accelerator, wherein the accelerator is to perform a first operation responsive to the native instruction sequence in parallel with performance of a second operation in the first core, the second operation independent from the first operation.

2. The processor of claim 1 , wherein the first core is to associate an event handler with a signal to be received from the accelerator to notify the first core upon completion of the first operation, and the first core is to execute the event handler after the notification, wherein the event handler is to receive and process result data from the first operation.

3. The processor of claim 1 , wherein the accelerator comprises a fixed function unit and the interface logic comprises a finite state machine (FSM) coupled to the fixed function unit.

4. The processor of claim 1 , wherein the first core is of a native instruction set architecture (ISA), and the accelerator is of a non-native ISA.

5. The processor of claim 1 , wherein the accelerator comprises a disabled system resource of a chipset to perform the graphics function but is disabled due to presence of an add-in graphics device to perform the graphics function.

6. The processor of claim 1 , wherein the interface logic comprises:
first logic to enable ingress communication of architectural state information to the accelerator and egress communication of status information to the first core; and
second logic to virtualize the accelerator.

7. The processor of claim 1 , wherein the accelerator includes:
a first portion to be used by the first core under the user-level control and without operating system (OS) support, and a second portion to be used via an operating system-enabled application.

8. A system comprising:
a graphics component to perform a graphics function;
a processor coupled to the graphics component including:
a first core to perform instructions via a first instruction set architecture (ISA);
a memory controller including an accelerator having duplicative functionality to the graphics component, wherein the accelerator comprises a graphics processor having a plurality of processing engines, at least some of the plurality of processing engines to be disabled for execution of the graphics function by configuration of the system according to a disable indicator programmed by a basic input/output system (BIOS), the at least some of the plurality of processing engines to execute a task unrelated to the graphics function responsive to a command from the first core; and

a dynamic random access memory (DRAM) coupled to the processor.

9. The system of claim 8 , wherein a user-level application is to use the accelerator to perform a first task different than the graphics function without operating system (OS) support.

10. The system of claim 8 , wherein the first core is to provide a virtual command to the accelerator and an interface of the memory controller is to map the virtual command into one or more instructions of a second instruction set architecture (ISA) associated with the accelerator.

11. The system of claim 8 , wherein the accelerator is a heterogeneous resource with respect to the first core and comprising a sequencer having next instruction pointer logic to determine a next instruction to be executed by the accelerator.

12. The system of claim 11 , further comprising an interface logic coupled to the accelerator to enable inter-sequencer communication between the first core and the accelerator by translation of the inter-sequencer communication, wherein the accelerator is to perform a first operation responsive to the inter-sequencer communication in parallel with performance of a second operation in the first core, the second operation independent from the first operation.

13. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
communicating architectural state information from a user-level application executing on a first core of a multi-core processor to an accelerator of the multi-core processor via a first user-level transfer instruction to configure the accelerator, wherein the accelerator comprises a heterogeneous resource with respect to the first core and having next instruction pointer logic to determine a next instruction to be executed by the accelerator, the heterogeneous resource comprising a graphics processor having a plurality of processing engines, at least some of the plurality of processing engines to be disabled for execution of a graphics function by configuration of a system including a graphics component to perform the graphics function according to a disable indicator programmed by a basic input/output system (BIOS), the at least some of the plurality of processing engines to execute a task unrelated to the graphics function responsive to a command from the first core;
communicating a request from the user-level application to the accelerator via a second user-level transfer instruction;
providing the request to the accelerator via an interface logic associated with the accelerator, wherein the interface logic translates the request to a native instruction sequence of the accelerator; and
performing a first function in the accelerator responsive to the request in parallel with a second function in the first core, the second function independent from the first function.

14. The non-transitory machine-readable medium of claim 13 , wherein communicating the request comprises sending the request to the interface logic and passing the request from the interface logic to the accelerator according to a private protocol between the interface logic and the accelerator.

15. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises sending the request to the interface logic via a first instruction set architecture, wherein the accelerator comprises a resource of a second instruction set architecture.

16. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises directly communicating the request without operating system (OS) support, wherein the accelerator is transparent to the OS, and wherein the first function is of a first user-level shred and the second function is of a second user-level shred, the first and second user-level shreds of the user-level application and scheduled by a first OS thread of a pl

Assignees

• Intel Corp

Inventors

• Wang Hong
• Shen John
• Jiang Hong
• Hankins Richard
• Hammarlund Per
• Rodgers Dion
• Chinya Gautham
• Patel Baiju
• Kaushik Shiv
• Bigbee Bryant
• Sheaffer Gad
• Talgam Yoav
• Yosef Yuval
• Held James P

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/3879

  for non-native instruction execution, e.g. executing a command; for Java instruction set · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title