Inter-processor interrupts

Patent metadata

Field	Value
Publication number	US-8984199-B2
Application number	US-63152203-A
Country	US
Kind code	B2
Filing date	Jul 31, 2003
Priority date	Jul 31, 2003
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.

First claim

What is claimed is:

1. A method comprising:
monitoring a first memory location by a first processor;
writing, by a second processor, an inter-processor interrupt request to the first memory location, wherein the first and second processors are general purpose processors of same type within a multi-processor computer system;
detecting, by the first processor, the inter-processor interrupt request in the first memory location, the first processor saving its state and executing a call instruction in response to the detecting, the call instruction specifying an address of an interrupt service routine to invoke said interrupt service routine, said address of said interrupt service routine having been made available to said first processor through a boot-up registration process;
performing, by the first processor, the interrupt service routine for the inter-processor interrupt request;
monitoring, by the second processor, a second, different memory location for acknowledgement of receipt of the inter-processor interrupt request; and
writing, by the first processor, to the second, different memory location to acknowledge receipt of the inter-processor interrupt request,
wherein the first memory location is accessible by a plurality of first processors, the plurality of first processors to monitor the first memory location to detect the inter-processor interrupt request, the first memory location being a single memory address.

2. The method of claim 1 , further comprising establishing by the first processor, a state for enabling ring transition on detection of the inter-processor interrupt request.

3. The method of claim 1 , wherein the first memory location is a linear memory location.

4. The method of claim 1 , wherein the first memory location is accessible by the first processor to monitor the first memory location.

5. The method of claim 1 , further comprising writing, by the second processor, the inter-processor interrupt request to a plurality of memory locations, each of the plurality of memory locations to be monitored by one or more processors.

6. The method of claim 1 , wherein the memory write to the first memory location is to a cached memory location.

7. A non-transitory machine-readable medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
monitoring a first memory location by a first processor;
writing, by a second processor, an inter-processor interrupt request to a first memory location, wherein the first and second processors are general purpose processors of same type within a multi-processor computer system;
detecting, by the first processor, the inter-processor interrupt request in the first memory location, the first processor saving its state and executing a call instruction in response to the detecting, the call instruction specifying an address of an interrupt service routine to invoke said interrupt service routine, said address of said interrupt service routine having been made available to said first processor through a boot-up registration process;
performing, by the first processor, the interrupt service routine for the inter-processor interrupt request;
monitoring, by the second processor, a second, different memory location for acknowledgement of receipt of the inter-processor interrupt request; and
writing, by the first processor, to the second memory location to acknowledge receipt of the inter-processor interrupt request,
wherein the first memory location is accessible by a plurality of first processors, the plurality of first processors to monitor the first memory location to detect the inter-processor interrupt request, the first memory location being a single memory address.

8. The medium of claim 7 , wherein the operations further comprise establishing, by the first processor, a state for enabling ring transition on detection of the inter-processor interrupt request.

9. The medium of claim 7 , wherein the first memory location is a linear memory location.

10. The medium of claim 7 , wherein the operations further comprise writing, by the second processor, the inter-processor interrupt request to a plurality of memory locations, each of the plurality of memory locations to be monitored by one or more processors.

11. The medium of claim 7 , wherein the memory write to the first memory location is to a cached memory location.

12. An apparatus comprising:
a first processor including an execution unit to cause a memory write to a first memory location; and
a second processor including circuitry to save said second processor's state and execute an instruction that causes a call to an interrupt service routine in response to detection of the memory write, the instruction that causes the call to the interrupt service routine to specify an address for the interrupt service routine, the address for the interrupt service routine to be provided to said second processor through a boot-up registration process, wherein the first and second processors are general purpose processors of a same type within a multi-processor computer system,
wherein the second processor is to write to a second, different memory location to acknowledge the memory write, and wherein the first processor is to monitor the second, different memory location for the acknowledgement, and wherein the first memory location is accessible by a plurality of second processors, the plurality of second processors to monitor the first memory location to detect the memory write.

13. The apparatus of claim 12 , wherein the call is to be registered at a boot time.

14. The apparatus of claim 12 , wherein the memory write is to a cached memory location.

15. The apparatus of claim 12 , wherein the state is to be saved in kernel mode.

Assignees

• Hammarlund Per
• Crossland James B
• Kaushik Shivnandan D
• Aggarwal Anil
• Intel Corp

Inventors

• Hammarlund Per
• Crossland James B
• Kaushik Shivnandan D
• Aggarwal Anil

Classifications

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title