Synchronization of interrupt processing to reduce power consumption

Patent metadata

Field	Value
Publication number	US-10089263-B2
Application number	US-201415118501-A
Country	US
Kind code	B2
Filing date	Mar 24, 2014
Priority date	Mar 24, 2014
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1. A processor comprising:
at least one core including a first core; and
interrupt delay logic to:
receive a first interrupt at a first time;
delay the first interrupt from being processed by a first time delay that begins at the first time unless the first interrupt is pending at a second time when a second interrupt is processed by the first core;
if the first interrupt is pending at the second time, indicate to the first core to begin to process the first interrupt prior to completion of the first time delay;
receive a third interrupt at a third time and assign to the third interrupt a second time delay;
delay processing of the third interrupt from the third time by the second time delay unless the third interrupt is pending while the first interrupt or the second interrupt is processed;
if the third interrupt is pending while the first interrupt or the second interrupt is processed, indicate to the first core to process the third interrupt without completion of the second time delay; and
if the third interrupt is not pending while the first interrupt or the second interrupt is processed, indicate to the first core to process the third interrupt after completion of the second time delay.

2. The processor of claim 1 , wherein when a plurality of received interrupts are pending at the second time, the first core is to process the plurality of pending interrupts during a first active period that commences at the second time, wherein the first core remains in an active state throughout the first active period.

3. The processor of claim 2 , wherein the first core is to transition from the active state to an inactive state after the second interrupt and the plurality of pending interrupts are processed.

4. The processor of claim 1 , wherein the first core is to remain in an active state while the first interrupt and the second interrupt are processed and to transition to an inactive state after the first interrupt and the second interrupt are processed.

5. The processor of claim 1 , wherein when the second interrupt is received periodically, for each occurrence of the second interrupt received the second interrupt is to be processed by the first core without intentional delay and the interrupt delay logic is to indicate to the first core that if there are additional pending interrupts, to begin to process the additional pending interrupts prior to completion of a corresponding time delay and while the first core remains in an active state.

6. The processor of claim 5 , further comprising, for each occurrence of receipt of the second interrupt, upon completion of processing of the second interrupt and the additional pending interrupts, the first core is to transition to an inactive state.

7. The processor of claim 1 , wherein the interrupt delay logic includes a counter to count the first time delay.

8. A system comprising:
a dynamic random access memory (DRAM); and
a processor comprising:
one or more cores;
an interrupt controller coupled to the one or more cores to direct each of one or more received interrupts to a first core of the one or more cores; and
an interrupt delay controller coupled to the interrupt controller, the interrupt delay controller including:
one or more delay counters to count a respective time delay to process a corresponding interrupt of a first interrupt type, wherein each delay counter is to commence a respective count upon receipt by the processor of the corresponding interrupt;
pending interrupt release logic to, responsive to a first interrupt being processed, send each pending interrupt of the first interrupt type to the interrupt controller prior to expiration of the respective time delay, wherein the interrupt delay controller is to send the first interrupt to the interrupt controller without intentional delay, the first interrupt of a second interrupt type;

wherein the interrupt delay controller is to:
delay processing of another interrupt of the first interrupt type by a respective time delay unless the another interrupt is pending while the first interrupt or the each pending interrupt of the first interrupt type is processed;
if the another interrupt is pending while the first interrupt or the each pending interrupt of the first interrupt type is processed, indicate to the first core to process the another interrupt without completion of the respective time delay; and
if the another interrupt is not pending while the first interrupt or the each pending interrupt of the first interrupt type is processed, indicate to the first core to process the another interrupt after completion of the respective time delay.

9. The system of claim 8 , wherein if no interrupt is processed during a respective time delay associated with a second interrupt of the first interrupt type, the interrupt delay controller is to send the second interrupt to the interrupt controller upon completion of the count of the corresponding delay counter.

10. The system of claim 8 , wherein when the count of a second delay counter completes, the pending interrupt release logic is to send each pending interrupt to the interrupt controller, to be processed while the first core is in the active state.

11. The system of claim 8 , wherein after the pending interrupts are processed the corresponding core is to become inactive.

12. The system of claim 8 , wherein the processor further includes interrupt detection logic to, upon receipt of a hard interrupt, send the hard interrupt to the interrupt controller without intentional delay.

13. The system of claim 8 , wherein the processor further includes counter assignment logic to assign a corresponding delay counter to each soft interrupt received.

14. A method comprising:
processing a first interrupt of a first interrupt type by a core of a processor commencing at a first time, the first interrupt processed without intentional delay:
assigning, by the processor, a time delay to a second interrupt of a second interrupt type received at a second time;
processing the second interrupt by the core after expiration of the time delay that begins at the second time, unless the second interrupt is pending at the first time;
if the second interrupt is pending at the first time, processing the second interrupt by the core prior to expiration of the time delay;
delaying processing of a third interrupt of the second interrupt type until expiration of a second time delay unless the third interrupt is pending while the first interrupt or the second interrupt is processed;
if the third interrupt is pending while the first interrupt or the second interrupt is processed, indicating to the core to process the third interrupt without completion of the second time delay; and
if the third interrupt is not pending while the first interrupt or the second interrupt is processed, indicating to the core to process the third interrupt after completion of the second time delay.

15. The method of claim 14 , wherein if the second interrupt is pending at the first time, processing the second interrupt while the core is in an active state responsive to processing of the first interrupt.

16. The method of claim 14 , further comprising after the first interrupt and the second interrupt are processed, transitioning the core to an inactive state.

17. The method of claim 14 , further comprising, if a plurality of interrupts of the second interrupt type are pending at the first time, sending the plurality of interrupts, prior to completion of a respective time delay of each of the plurality of interrupts, to the core to be proces

Assignees

• Intel Corp
• Loh Thiam Wah
• Chinya Gautham N
• Hammarlund Per
• Fortas Reza
• Wang Hong
• Sun Huajin

Inventors

• Loh Thiam Wah
• Chinya Gautham N
• Hammarlund Per
• Fortas Reza
• Wang Hong
• Sun Huajin

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2213/2404

  Generation of an interrupt or a group of interrupts after a predetermined number of interrupts · CPC title

• G06F2213/2406

  Generation of an interrupt or a group of interrupts after a fixed or calculated time elapses · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title