Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Patent metadata

Field	Value
Publication number	US-10452403-B2
Application number	US-201514866875-A
Country	US
Kind code	B2
Filing date	Sep 26, 2015
Priority date	Jun 30, 2005
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

First claim

We claim:

1. A processor comprising:
a plurality of simultaneous multithreading (SMT) cores to simultaneously execute a plurality of threads; and
a first core of the plurality of SMT cores comprising:
a first set of instruction processing resources to execute a first thread;
a second set of instruction processing resources to execute a second thread; and
thread management hardware to:
in response to the first set of processing resources encountering a resource-not available event during execution of the first thread, migrate the first thread in its entirety from the first set of instruction processing resources to the second set of instruction processing resources to execute based on characteristics of one or more instructions to be executed, wherein the characteristics of one or more instructions make the second set of instruction processing resources execute the first thread more efficiently due to availability of one or more functional units that are for floating-point operations and that are within the second set of instruction processing resources, and wherein the migration from the first set of instruction processing resources to the second set of instruction processing resources is performed automatically without intervention from an operating system; and
in response to completion of execution of the first thread by the second set of instruction processing resources using the functional units that are for floating-point operations, transfer back the first thread to the first set of instruction processing resources.

2. The processor as in claim 1 further comprising: a set of registers for storing data for the first and second threads.

3. The processor as in claim 1 , further comprising: an instruction fetch logic to fetch the one or more instructions.

4. The processor as in claim 1 , wherein the first and second sets of instruction processing resources are to be identified by identifiers (IDs).

5. The processor as in claim 1 , wherein the one or more instructions specifies a condition or an event to cause the migration.

6. The processor as in claim 5 , wherein the condition or the event is one or more of a trap, a page fault, and a system call.

7. The processor as in claim 1 , wherein the first set of instruction processing resources is operating system sequestered.

8. The processor as in claim 1 , wherein the one or more instructions include a control transfer instruction.

9. A system comprising:
a memory to store an operating system; and
a processor coupled to the memory, the processor comprising:
a plurality of simultaneous multithreading (SMT) cores to simultaneously execute a plurality of threads; and
a first core of the plurality of SMT cores comprising:
a first set of instruction processing resources to execute a first thread;
a second set of instruction processing resources to execute a second thread; and
thread management hardware to:
in response to the first set of processing resources encountering a resource-not available event during execution of the first thread, migrate the first thread in its entirety from the first set of instruction processing resources to the second set of instruction processing resources to execute based on characteristics of one or more instructions to be executed, wherein the characteristics of one or more instructions make the second set of instruction processing resources execute the first thread more efficiently due to availability of one or more functional units that are for floating-point operations and that are within the second set of instruction processing resources, and wherein the migration from the first set of instruction processing resources to the second set of instruction processing resources is performed automatically without intervention from an operating system; and
in response to completion of execution of the first thread by the second set of instruction processing resources using the functional units that are for floating-point operations, transfer back the first thread to the first set of instruction processing resources.

10. The system as in claim 9 , wherein the processor further comprises:
a set of registers for storing data for the first and second threads.

11. The system as in claim 9 , wherein the processor further comprises:
an instruction fetch logic to fetch the one or more instructions.

12. The system as in claim 9 , wherein each the first and second sets of instruction processing resources are to be identified by identifiers (IDs).

13. The system as in claim 9 , wherein the one or more instructions specifies a condition or an event to cause the migration.

14. The system as in claim 13 , wherein the condition or the event is one or more of a trap, a page fault, and a system call.

15. The system as in claim 9 , wherein the first set of instruction processing resources is operating system sequestered.

16. The system as in claim 9 , wherein the one or more instructions include a control transfer instruction.

Assignees

• Intel Corp

Inventors

• Wang Hong
• Shen John P
• Grochowski Edward T
• Hankins Richard A
• Chinya Gautham N
• Bigbee Bryant E
• Kaushik Shivnandan D
• Zou Xiang Chris
• Hammarlund Per
• Rodgers Scott Dion
• Tian Xinmin
• Aggawal Anil
• Sethi Prashant
• Patel Baiju V
• Held James P

Classifications

• G06F9/3867 Primary

  using instruction pipelines · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title