Fill of vias in single and dual damascene structures using self-assembled monolayer

Patent metadata

Field	Value
Publication number	US-12598977-B2
Application number	US-202117558423-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

First claim

What is claimed is:

1 . An integrated circuit device, comprising:
a first metallization level comprising a metallization feature; a second metallization level over the first metallization level, the second metallization level comprising a metal via on the metallization feature and a metal line on the metal via, wherein the metal via and the metal line are within an interlayer dielectric material, the metal via comprising a first portion on the metallization feature and a second portion on the first portion, the first portion comprising a first metal and the second portion comprising the first metal or a second metal; and a layer between the first portion of the metal via and the interlayer dielectric material, the layer comprising a plurality of molecules having at least head groups coupled to the interlayer dielectric material and tails distal the interlayer dielectric material, wherein the second portion of the metal via is on the interlayer dielectric material and the first portion has a width that is less than a width of the second portion.

2 . The integrated circuit device of claim 1 , wherein the molecules of the layer comprise at least one of a fluorinated alkyl silane, an alkyl chlorosilane, a phosphonate, or an aminosilane.

3 . The integrated circuit device of claim 1 , wherein the molecules of the layer comprise at least one of 1H, 1H, 2H, 2H-perfluorooctyltrichlorosilane, (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane, octadecyltrichlorosilane, octadecylphosphonic acid, bis(N,N-dimethylamino)dimethylsilane, or (N,N-dimethylamino)trimethylsilane.

4 . The integrated circuit device of claim 1 , wherein the first portion of the metal via comprises at least one of fluorine, chlorine, phosphorous, carbon, hydrogen, or nitrogen.

5 . The integrated circuit device of claim 1 , wherein the second portion of the metal via comprises the second metal.

6 . The integrated circuit device of claim 5 , wherein the first portion of the metal via has a height that is less than a height of the second portion.

7 . The integrated circuit device of claim 5 , wherein the metal line comprises the second metal.

8 . The integrated circuit device of claim 7 , wherein the metal line comprises a liner comprising one of tantalum, tantalum and nitrogen, titanium, titanium and nitrogen, or tantalum and cobalt and a fill metal comprising the second metal, and wherein the fill metal is on the second portion of the metal via.

9 . The integrated circuit device of claim 8 , wherein the liner extends between the interlayer dielectric material and the second portion of the metal via.

10 . The integrated circuit device of claim 7 , wherein the first metal comprises one of cobalt, tungsten, titanium, aluminum, molybdenum, or ruthenium, and wherein the second metal comprises copper.

11 . The integrated circuit device of claim 1 , further comprising:
an integrated circuit die comprising the first metallization level, the second metallization level, and the layer; and a power supply coupled to the integrated circuit die.

12 . An integrated circuit device, comprising:
a first metallization level comprising a metallization feature; a second metallization level comprising a metal via and a metal line within an interlayer dielectric material, the metal via comprising a first portion on the metallization feature and a second portion on the first portion, the first portion comprising a first metal and the second portion comprising the first metal or a second metal; and a layer between the first portion and the interlayer dielectric material, the layer comprising a plurality of molecules having at least head groups coupled to the interlayer dielectric material and tails distal the interlayer dielectric material, wherein the second portion is on the interlayer dielectric material, and the first portion has a width that is less than a width of the second portion.

13 . The integrated circuit device of claim 12 , wherein the molecules of the layer comprise at least one of a fluorinated alkyl silane, an alkyl chlorosilane, a phosphonate, or an aminosilane.

14 . The integrated circuit device of claim 12 , wherein the molecules of the layer comprise at least one of 1H, 1H, 2H, 2H-perfluorooctyltrichlorosilane, (heptadecafluoro-1,1,2,2-tetrahydrodecyl)triethoxysilane, octadecyltrichlorosilane, octadecylphosphonic acid, bis(N,N-dimethylamino)dimethylsilane, or (N,N-dimethylamino)trimethylsilane.

15 . The integrated circuit device of claim 12 , wherein the first portion comprises at least one of fluorine, chlorine, phosphorous, carbon, hydrogen, or nitrogen.

16 . The integrated circuit device of claim 12 , wherein the second portion comprises the second metal.

17 . The integrated circuit device of claim 16 , wherein the first portion has a height that is less than a height of the second portion.

18 . The integrated circuit device of claim 16 , wherein the metal line comprises the second metal.

19 . The integrated circuit device of claim 18 , wherein the metal line comprises a liner comprising one of tantalum, tantalum and nitrogen, titanium, titanium and nitrogen, or tantalum and cobalt and a fill metal comprising the second metal, wherein the fill metal is on the second portion.

20 . The integrated circuit device of claim 19 , wherein the liner extends between the interlayer dielectric material and the second portion.

21 . The integrated circuit device of claim 18 , wherein the first metal comprises one of cobalt, tungsten, titanium, aluminum, molybdenum, or ruthenium, and wherein the second metal comprises copper.

22 . The integrated circuit device of claim 12 , further comprising:
an integrated circuit die comprising the first metallization level, the second metallization level, and the layer; and a power supply coupled to the integrated circuit die.

Assignees

• Intel Corp

Inventors

• Chen Jiun-Ruey
• Jezewski Christopher
• Plombon John
• Reshotko Miriam
• Kobrinsky Mauro
• Clendenning Scott B

Classifications

• H10W20/4473

  Conductive organic materials, e.g. conductive adhesives or conductive inks · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title