Self-assembled monolayer on a dielectric for transition metal dichalcogenide growth for stacked 2d channels

Patent metadata

Field	Value
Publication number	US-2023420510-A1
Application number	US-202217850078-A
Country	US
Kind code	A1
Filing date	Jun 27, 2022
Priority date	Jun 27, 2022
Publication date	Dec 28, 2023
Grant date	—

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A transistor structure, comprising:
a plurality of channels, wherein each of the plurality of channels is a monolayer, and wherein the plurality of channels are in a stacked formation; one or more dielectric layers, respectively, separating each of the plurality of channels; and wherein a particle proximate to a surface of one of the one or more dielectric layers adjacent to one of the plurality of channels includes a selected one or more of: fluorine, chlorine, phosphorus, or nitrogen.

2 . The transistor structure of claim 1 , wherein each of the plurality of channels is a transition metal dichalcogenide (TMD) monolayer.

3 . The transistor structure of claim 1 , wherein the plurality of channels overlap each other in a direction perpendicular to a plane of one of the plurality of channels.

4 . The transistor structure of claim 1 , further comprising one or more metal layers adjacent, respectively, to the one or more dielectric layers.

5 . The transistor structure of claim 1 , wherein the plurality of channels are grown using a metal oxide chemical vapor deposition (MOCVD) process.

6 . The transistor structure of claim 1 , wherein another particle proximate to a surface of the one of the one or more dielectric layers adjacent to the one of the plurality of channels includes oxygen.

7 . The transistor structure of claim 1 , wherein a width of the each of the plurality of channels is between 5 and 50 nanometers.

8 . The transistor structure of claim 1 , further comprising:
a source at a first end of the plurality of channels and the one or more dielectric layers; and a drain at a second end of the plurality of channels and the one or more dielectric layers opposite the first end.

9 . The transistor structure of claim 1 , further comprising a wafer;
wherein one of the plurality of channels is on the wafer; and wherein the wafer includes a self-assembled monolayer (SAM) material.

10 . A die comprising:
a substrate; and a transistor structure on the substrate, the transistor structure including: a first dielectric layer on a metal layer; a second dielectric layer above the first dielectric layer; and wherein a side of the first dielectric layer has a first area and a second area, wherein the first area and the second area are separate and distinct, and wherein the second area includes oxygen atoms.

11 . The die of claim 10 , wherein a density of oxygen atoms on the second area of the side of the first dielectric layer is greater than a density of oxygen atoms on the first area of the side of the first dielectric layer.

12 . The die of claim 10 , further including a transition metal dichalcogenide (TMD) layer on the second area of the side of the first dielectric layer.

13 . The die of claim 12 , further comprising a dielectric on the first area of the side of the first dielectric layer.

14 . The die of claim 10 , wherein a side of the second dielectric layer has a first area and a second area, wherein the first area and the second area are separate and distinct, and wherein the second area includes oxygen atoms.

15 . The die of claim 14 , wherein a density of oxygen atoms on the second area of the side of the second dielectric layer is greater than a density of oxygen atoms on the first area of the side of the second dielectric layer.

16 . The die of claim 14 , further including a TMD layer on the second area of the side of the second dielectric layer.

17 . The die of claim 16 , further comprising a dielectric on the first area of the side of the first dielectric layer.

18 . An apparatus comprising:
a wafer; and a transistor structure on the wafer, the transistor structure including:
a first dielectric layer on a metal layer;
a gap layer on the first dielectric layer;
a second dielectric layer above the gap layer; and
a seed material on the first dielectric layer, the seed material extending into the gap layer.

19 . The apparatus of claim 18 , wherein the seed material includes a selected one or more of: tungsten oxide (WO x ) or molybdenum oxide (MoO x ).

20 . The apparatus of claim 18 , further comprising a growth promoter on the first dielectric layer surrounding the seed material.

21 . The apparatus of claim 18 , wherein the growth promoter includes a selected one or more of: carbon or sodium.

22 . A method comprising:
providing a transistor structure, the transistor structure including a plurality of substructures stacked on each other, each of the substructure including:
a first dielectric layer on a metal layer;
a gap layer on the first dielectric layer; and
a second dielectric layer above the gap layer; and
depositing a self-assembled monolayer (SAM) material on the transistor structure, wherein the SAM material is partially deposited on each of the first dielectric layers and extends into each of the gap layers.

23 . The method of claim 22 , further comprising growing a transition metal dichalcogenide (TMD) on a portion of the first dielectric layers that does not have deposited SAM material.

24 . The method of claim 22 , further comprising:
applying an oxygen plasma to the transistor structure; and growing a TMD on a portion of each of the first dielectric layers where the SAM material was not deposited.

25 . The method of claim 22 , further comprising:
applying a seed on a portion of each of the first dielectric layers; applying a growth promoter on each of the first dielectric layers surrounding the seed; and growing a TMD on each of the first dielectric layers.

Assignees

• Intel Corp

Inventors

• Naylor Carl H
• Maxey Kirby
• O'Brien Kevin P
• Dorow Chelsey
• Lee Sudarat
• Penumatcha Ashish Verma
• Avci Uygar E
• Metz Matthew V
• Clendenning Scott B
• Chen Jiun-Ruey
• Lin Chia-Ching
• Rogan Carly

Classifications

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10P14/3246

  Monolayers · CPC title

• H10P14/3236

  being chalcogenide semiconducting materials not being oxides, e.g. ternary compounds · CPC title

• H10D62/84

  being selenium or tellurium only · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title