Interconnect structures with area selective adhesion or barrier materials for low resistance vias in integrated circuits

Patent metadata

Field	Value
Publication number	US-2022139772-A1
Application number	US-202017087523-A
Country	US
Kind code	A1
Filing date	Nov 2, 2020
Priority date	Nov 2, 2020
Publication date	May 5, 2022
Grant date	—

Abstract

Integrated circuit interconnect structures including an interconnect metallization feature with a liner material of a greater thickness between a fill metal and dielectric material, and of a lesser thickness between the fill metal and a lower-level interconnect metallization feature. The liner material may be substantially absent from an interface between the fill metal and the lower-level interconnect metallization feature. Liner material of reduced thickness at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive liner material that may enhance the scalability of interconnect structures. In some embodiments, liner material is deposited upon dielectric surfaces with an area selective atomic layer deposition process. For single damascene implementations, both a via and a metal line may include a selectively deposited liner material.

First claim

What is claimed is:

1 . A integrated circuit (IC) interconnect structure, comprising:
a first line metallization; a dielectric material over the first line metallization; a via metallization through the dielectric material, and coupled to the first line metallization; and a second line metallization over, and coupled to, the first line metallization through the via metallization, wherein the second line metallization comprises:
a fill metal;
a first thickness of a liner material between a bottom of the fill metal and the dielectric material; and
a second thickness of the liner material between a bottom of the fill metal and the via metallization, wherein the second thickness is less than half of the first thickness, and comprises a higher atomic concentration of C, P, or B than the first thickness of the liner material.

2 . The IC interconnect structure of claim 1 , wherein the first thickness is at least 2 nm, and the second thickness is less than 20% of the first thickness.

3 . The IC interconnect structure of claim 1 , wherein the second thickness is less than 1 nm.

4 . The IC interconnect structure of claim 2 , wherein the liner material comprises at least one of Ta, Mo, or W.

5 . The IC interconnect structure of claim 4 , wherein the liner material further comprises nitrogen.

6 . The IC interconnect structure of claim 5 , wherein the first thickness of the liner material comprises predominantly Ta, and N.

7 . The IC interconnect structure of claim 5 , wherein the second thickness of the liner material or the barrier material comprises C.

8 . The IC interconnect structure of claim 1 , wherein the via metallization comprises the fill metal, and the via metallization comprises a third thickness of the liner material in physical contact with the dielectric material.

9 . The IC interconnect structure of claim 8 , wherein a fourth thickness of the liner material is between the fill metal of the via metallization and the first line metallization.

10 . The IC interconnect structure of claim 9 , wherein the third thickness is at least 2 nm, and the fourth thickness is less than 20% of the third thickness.

11 . The IC interconnect structure of claim 10 , wherein the fourth thickness is less than 1 nm.

12 . The IC interconnect structure of claim 11 , wherein the third thickness is substantially equal to the first thickness and the fourth thickness is substantially equal to the second thickness.

13 . The IC interconnect structure of claim 1 , wherein the fill metal comprises Cu, and the via metallization comprises at least one of Cu, W, or Ru.

14 . A computer platform comprising:
a power supply; and an integrated circuit (IC) coupled to the power supply, wherein the IC comprises:
a device layer comprising a plurality of transistors comprising one or more semiconductor materials; and
a plurality of interconnect levels, the interconnect levels further comprising:
a first line metallization;
a dielectric material over the first line metallization;
a via metallization through the dielectric material, and coupled to the first line metallization; and
a second line metallization over, and coupled to, the first line metallization through the via metallization, wherein the second line metallization comprises:
a fill metal;
a first thickness of a liner material between the fill metal and the dielectric material; and
a second thickness of the liner material between the fill metal and the via metallization, wherein the second thickness is less than half of the first thickness, and comprises a higher atomic concentration of C, P, or B than the first thickness of the liner material.

15 . The computer platform of claim 14 , wherein the IC comprises a microprocessor.

16 . A method of fabricating an integrated circuit (IC) interconnect structure, the method comprising:
exposing a region of a metallization feature by forming at least one of a via opening or a trench in a dielectric material; forming, with a selective atomic layer deposition (ALD) process, a first thickness of a liner material upon a surface of the dielectric material, and a second thickness of the liner material upon a surface of the metallization feature, wherein the second thickness is less than half of the first thickness, and comprises a higher atomic concentration of C, P, or B than the first thickness of the liner material; depositing a fill metal within the via opening or the trench; and planarizing the fill metal with the dielectric material.

17 . The method of claim 16 , wherein the ALD process comprises:
reacting metallic material surfaces with an inhibitor; reacting dielectric surfaces with a metallic precursor; and reacting the metallic precursor with a co-reactant to form a metallic material.

18 . The method of claim 17 , wherein the metallic material comprises Ta and N.

19 . The method of claim 17 , wherein the inhibitor comprises at least one of C, B, or P.

20 . The method of claim 19 , wherein the inhibitor comprises aniline.

21 . The method of claim 19 , wherein forming the second thickness of the liner material comprises forming the metallic material doped with the at least one of C, B, or P.

22 . The method of claim 21 , further comprises forming a self-assembled monolayer (SAM) on the surface of the metallization feature prior to performing the selective ALD process.

Assignees

• Intel Corp

Inventors

• Jezewski Christoper
• Chen Jiun-Ruey
• Reshotko Miriam
• Blackwell James M
• Metz Matthew
• Lin Che-Yun

Classifications

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/076

  in via holes or trenches · CPC title