Selective conductive cap and liner deposition techniques for interconnects and contact structures

US2025379149A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025379149-A1
Application numberUS-202418735768-A
CountryUS
Kind codeA1
Filing dateJun 6, 2024
Priority dateJun 6, 2024
Publication dateDec 11, 2025
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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Selective metal capping and/or liner materials and processes described herein may enable hermetically encapsulating metal interconnects and metal-silicon interfaces in transistor contacts. In one example, an IC structure includes an interconnect layer with a conductive interconnect that is lined with a ruthenium-based liner, and capped with a selectively deposited cap that includes one or more of ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, and niobium individually or in an alloy. In another example, an IC structure includes a transistor contact structure with a selectively deposited conductive cap over an interface material, where the conductive cap material is absent or substantially thinner on sidewalls of the contact opening. In one example, the conductive cap material over the Si-metal interface includes one or more of ruthenium, molybdenum, tungsten, rhodium, iridium, platinum, rhenium, cobalt, and niobium individually or in combination.

First claim

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1 . An integrated circuit (IC) structure, comprising: a region of a doped semiconductor material, wherein the region is either a source region or a drain region of a transistor; and a contact structure coupled with the region, wherein the contact structure includes: a first conductive material in an opening in an insulator material, an interface material between the region and the first conductive material, and a second conductive material including ruthenium between the interface material and the first conductive material, wherein: the second conductive material has a first thickness at a bottom of the opening, and a thickness of the second conductive material on sidewalls of the opening is at most 15% of the first thickness. 2 . The IC structure of claim 1 , wherein: the second conductive material is substantially absent from the sidewalls of the opening. 3 . The IC structure of claim 1 , further comprising: a layer of the second conductive material on the sidewalls of the opening, wherein: the layer has the thickness, and a ratio of the first thickness to the thickness is in a range of about 7:1 and 10:1. 4 . The IC structure of claim 1 , wherein: the first thickness is a dimension of the second conductive material at a bottom of the opening in a plane substantially orthogonal to a substrate over which the region is disposed, and the first thickness is in a range of about 4-10 nanometers. 5 . The IC structure of claim 1 , further comprising: a liner between the insulator material and the first conductive material, wherein the liner includes a metal and has a different material composition than the first conductive material and the second conductive material. 6 . The IC structure of claim 5 , wherein: the second conductive material is present on the sidewalls of the opening; and the liner is between the second conductive material and the first conductive material. 7 . The IC structure of claim 1 , wherein: the second conductive material further includes one or more of: molybdenum, tungsten, rhodium, iridium, rhenium, niobium, and cobalt. 8 . The IC structure of claim 1 , wherein: the interface material is present on the sidewalls of the opening; and the second conductive material is present on the sidewalls of the opening between the interface material and the first conductive material. 9 . The IC structure of claim 8 , wherein: the interface material at a bottom of the opening has a third thickness; the interface material on the sidewalls of the opening has a fourth thickness; and a ratio of the third thickness to the fourth thickness is in a range of about 3.5:1 to 10:1. 10 . An integrated circuit (IC) structure, comprising: a first layer including a region of a doped semiconductor material; a second layer including a conductive interconnect; and a contact structure between and coupled with the region and the conductive interconnect, wherein the contact structure includes: a fill material, an interface material between the region and the fill material, wherein the interface material includes a semiconductor material and a metal, and a conductive material between the interface material and the fill material, wherein the conductive material includes ruthenium. 11 . The IC structure of claim 10 , wherein: the conductive material of the contact structure is substantially limited to an area between the fill material and the interface material. 12 . The IC structure of claim 10 , wherein: the contact structure is in an opening in an insulator material; and the conductive material is substantially absent from sidewalls of the opening. 13 . The IC structure of claim 10 , wherein: the contact structure is in an opening in an insulator material; the IC structure further comprises a liner of the conductive material on sidewalls of the opening; the conductive material has a first thickness between the interface material and the fill material and a second thickness on the sidewalls of the opening; and a ratio of the first thickness to the second thickness is in a range of about 7:1 and 10:1. 14 . The IC structure of claim 13 , wherein: a thickness of the conductive material between the interface material and the fill material is in a range of about 4-10 nanometers. 15 . The IC structure of claim 13 , wherein the liner is a first liner and wherein the IC structure further comprises: a second liner on the sidewalls of the opening between the first liner and the fill material, wherein the second liner includes a metal and has a different material composition than the first liner. 16 . The IC structure of claim 10 , wherein: the conductive material further includes one or more of: molybdenum, tungsten, rhodium, iridium, rhenium, niobium, and cobalt. 17 . The IC structure of claim 10 , wherein: the contact structure is in an opening in an insulator material; and the IC structure further comprises: a liner of the conductive material on sidewalls of the opening, and a layer of the interface material on the sidewalls of the opening between the insulator material and the liner. 18 . The IC structure of claim 17 , wherein: the interface material at a bottom of the opening has a first thickness; the interface material on the sidewalls of the opening has a second thickness; and the first thickness is greater than the second thickness. 19 . An integrated circuit (IC) structure, comprising: a device region; and an interconnect layer over the device region, wherein the interconnect layer includes: an insulator material, a conductive interconnect in an opening in the insulator material, wherein the conductive interconnect includes a first conductive material, a liner on sidewalls of the opening, wherein the liner includes ruthenium, and a second conductive material over the first conductive material and over the liner, wherein the second conductive material includes ruthenium. 20 . The IC structure of claim 19 , wherein: the liner has a first thickness, wherein the first thickness is a dimension of the liner on the sidewalls of the opening in a first plane substantially parallel to the device region; and the second conductive material has a second thickness in a range of about one to two times the first thickness, wherein the second thickness is a dimension of the second conductive material in a second plane substantially orthogonal to the first plane.

Assignees

Inventors

Classifications

  • in via holes or trenches · CPC title

  • by selectively depositing, e.g. by using selective CVD or plating · CPC title

  • Vias, e.g. via plugs · CPC title

  • the barrier, adhesion or liner layers being within a main fill metal · CPC title

  • H10W20/425Primary

    Barrier, adhesion or liner layers · CPC title

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What does patent US2025379149A1 cover?
Selective metal capping and/or liner materials and processes described herein may enable hermetically encapsulating metal interconnects and metal-silicon interfaces in transistor contacts. In one example, an IC structure includes an interconnect layer with a conductive interconnect that is lined with a ruthenium-based liner, and capped with a selectively deposited cap that includes one or more …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 11 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).