Staggered vertically spaced integrated circuit line metallization with differential vias & metal-selective deposition

Patent metadata

Field	Value
Publication number	US-2023197602-A1
Application number	US-202117560085-A
Country	US
Kind code	A1
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Jun 22, 2023
Grant date	—

Abstract

Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.

First claim

What is claimed is:

1 . An integrated circuit (IC) interconnect structure, comprising:
a plurality of first interconnect lines within a first plane of the structure and having a pitch; a plurality of second interconnect lines within a second plane of the structure, over the first plane, wherein individual ones of the second interconnect lines comprise a cap material over a fill material, and are laterally staggered from the first interconnect lines by less than the pitch; and a plurality of interconnect vias within a third plane of the structure, over the second plane, wherein a first of the interconnect vias intersects one of the first interconnect lines and wherein a second of the interconnect vias intersects one of the second interconnect lines.

2 . The IC interconnect structure of claim 1 , wherein:
a dielectric material is between individual ones of the second interconnect lines; the first of the interconnect vias passes through the dielectric material; and the cap material comprises a metal.

3 . The IC interconnect structure of claim 2 , wherein the cap material comprises predominantly Ru, Co, Mo, W, Ni, Pd or Ir.

4 . The IC interconnect structure of claim 3 , wherein the fill material is predominantly Cu and the cap material comprises predominantly Co, Mo, W, Ni, Pd or Ir.

5 . The IC interconnect structure of claim 3 , wherein the fill material is predominantly W and the cap material comprises predominantly Ru, Co, Mo, Ni, Pd or Ir.

6 . The IC interconnect structure of claim 3 , wherein the fill material is predominantly Ru and the cap material comprises predominantly Mo or W.

7 . The IC interconnect structure of claim 1 , wherein:
the second interconnect lines are substantially parallel to the first interconnect lines; the first plane does not pass through the second interconnect lines; the second plane does not pass through the first interconnect lines; and individual ones of the second interconnect lines are laterally staggered from the first interconnect lines by approximately half the pitch.

8 . The IC interconnect structure of claim 1 , wherein the cap material is substantially absent from the first interconnect lines.

9 . The IC interconnect structure of claim 1 , wherein the second of the interconnect vias is in direct contact with the fill material.

10 . The IC interconnect structure of claim 1 , wherein the cap material is between the fill material and the second of the interconnect vias.

11 . An integrated circuit (IC) structure, comprising:
a device layer comprising a plurality of transistors comprising a semiconductor material; and an interconnect level over the device layer, wherein the interconnect level further comprises:
a plurality of first interconnect lines within a first plane of the structure and having a pitch;
a plurality of second interconnect lines within a second plane of the structure, over the first plane, wherein individual ones of the second interconnect lines comprise a cap material over a fill material, and are laterally staggered from the first interconnect lines by less than the pitch; and
a plurality of interconnect vias within a third plane of the structure, over the second plane, wherein a first of the interconnect vias intersects one of the first interconnect lines and wherein a second of the interconnect vias intersects one of the second interconnect lines.

12 . A computer platform comprising:
a power supply; and the IC structure of claim 11 coupled to the power supply.

13 . A method of fabricating an interconnect structure, the method comprising:
forming interconnect lines within one or more first dielectric materials, wherein a first plurality of the interconnect lines is within a first plane of the structure and has a pitch, and wherein a second plurality of the interconnect lines is within a second plane of the structure, and is laterally staggered from the first plurality by less than the pitch; depositing a cap material upon a surface of the second plurality of interconnect lines; depositing a second dielectric material over cap material and over the first dielectric materials; etching a plurality of vias through the second dielectric material, wherein a first of the vias exposes the cap material; advancing a second of the vias through a least a partial thickness of the first dielectric materials; and depositing conductive material within the first of the vias and the second of the vias.

14 . The method of claim 13 , wherein depositing the cap material comprises selectively depositing a metal upon the second plurality of interconnect lines.

15 . The method of claim 14 , wherein selectively depositing the metal further comprises depositing predominantly Ru, Co, Mo, W, Ni, Pd or Ir.

16 . The method of claim 15 , wherein selectively depositing the metal further comprises inhibiting an exposed surface of the first dielectric materials with a self-assembled monolayer.

17 . The method of claim 15 , wherein:
the second interconnect lines comprise predominantly Cu, and selectively depositing the metal further comprises depositing predominantly Co, Mo, W, Ni, Pd or Ir; or the second interconnect lines comprise predominantly W, and selectively depositing the metal further comprises depositing predominantly Ru, Co, Mo, Ni, Pd or Ir; or the second interconnect lines comprise predominantly Ru, and selectively depositing the metal further comprises depositing predominantly Mo or W.

18 . The method of claim 13 , wherein depositing conductive material within the first of the vias and the second of the vias comprises depositing a via metal and planarizing the metal with a surface of the second dielectric material.

19 . The method of claim 18 , wherein the via metal within the first of the vias is in direct contact with cap material.

20 . The method of claim 13 , further comprising forming a device layer comprising a plurality of transistors comprising a semiconductor material, and wherein the staggered interconnect lines are coupled to the transistors.

Assignees

• Intel Corp

Inventors

• Karpov Elijah
• Reshotko Miriam
• Clendenning Scott B
• Chen Jiun-Ruey
• Metz Matthew

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/48

  Insulating materials thereof · CPC title