Subtractively patterned interconnect structures for integrated circuits

Patent metadata

Field	Value
Publication number	US-12482744-B2
Application number	US-202418668038-A
Country	US
Kind code	B2
Filing date	May 17, 2024
Priority date	Nov 2, 2020
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

First claim

What is claimed is:

1 . An integrated circuit (IC) structure comprising:
a plurality of transistors; and an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
a via and a dielectric material adjacent to the via;
a line in direct physical contact with the via, wherein the line extends over the dielectric material, and wherein a top width of the line is smaller than a bottom width of the line, wherein the via has a first chemical composition and the line has a second composition, different than the first chemical composition; and
a bottom barrier material between the line and the dielectric material.

2 . The IC structure of claim 1 , wherein the line comprises at least a first of Cu, W, Ru, Co, Mo, W, Ir, Rh, or Pt, and wherein the via comprises at least a second of Ru, Co, Mo, W, Ir, Rh, Pt, Al or Cu.

3 . The IC structure of claim 1 , wherein the bottom barrier material comprises Ta and N.

4 . The IC structure of claim 1 , further comprising a sidewall barrier material in physical contact with a sidewall of the line, wherein the sidewall barrier material has a different composition than the bottom barrier material.

5 . The IC structure of claim 4 , wherein the sidewall barrier material is over, and, in physical contact with, a top of the line.

6 . The IC structure of claim 4 , wherein the sidewall barrier material comprises graphene, a metal chalcogenide, a metal oxide, a metallic compound comprising predominantly one of Ta, Co, or Ru, or a dielectric comprising silicon and at least one of nitrogen, or oxygen.

7 . The IC structure of claim 4 , wherein the line is a first line, the IC structure further comprises a second line adjacent to the first line, and the IC structure further comprises a second dielectric material over the first line and over the second line, wherein the second dielectric material has a different composition than the sidewall barrier material.

8 . The IC structure of claim 7 , wherein the second dielectric material spans a void between the sidewall barrier material on the sidewall of the first line and the sidewall barrier material on a sidewall of the second line.

9 . The IC structure of claim 8 , wherein the second dielectric material is between the void and the sidewall of the first line and the sidewall of the second line.

10 . The IC structure of claim 1 , further comprising a cap material on a top of the line, wherein the cap material has a different composition than the bottom barrier material.

11 . The IC structure of claim 10 , wherein the line is a first line and the cap material is a first cap material, the IC structure further comprises a second line, adjacent to the first line, and the IC structure further comprises a second cap material on the second line, wherein the first cap material has a first composition and the second cap material has a second composition, different than the first composition.

12 . The IC structure of claim 10 , further comprising a sidewall barrier material in physical contact with a sidewall of the line and in physical contact with a sidewall of the cap material.

13 . An integrated circuit (IC) structure comprising:
a plurality of transistors; and an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
a line extending a length in a first direction, wherein a first portion of the line is under a dielectric material; and
a via adjacent to the dielectric material and comprising a second portion of the line that is taller than the first portion of the line, wherein a top width of the via is smaller than a bottom width of the line that comprises a bottom barrier material.

14 . The IC structure of claim 13 , further comprising a sidewall barrier material in physical contact with a sidewall of the line, wherein the sidewall barrier material has a different composition than the bottom barrier material.

15 . The IC structure of claim 14 , wherein the bottom barrier material comprises Ta and N, and wherein the sidewall barrier material comprises graphene, a metal chalcogenide, a metal oxide, a metallic compound comprising predominantly one of Ta, Co, or Ru, or a dielectric comprising silicon and at least one of nitrogen, or oxygen.

16 . The IC structure of claim 14 , wherein the sidewall barrier material is in physical contact with a sidewall of the line.

17 . The IC structure of claim 16 , wherein the sidewall barrier material is over, and, in physical contact with the first portion of the line but absent from a top surface of the via.

18 . A method, comprising:
receiving a workpiece with a lower level interconnect metallization feature coplanar with an adjacent dielectric material; depositing a bottom barrier material layer upon the dielectric material; depositing an interconnect material layer over the lower level interconnect metallization feature and in physical contact with the bottom barrier material layer; and subtractively patterning the interconnect material layer and the bottom barrier material layer into an interconnect metallization line.

19 . The method of claim 18 , the method further comprising depositing a sidewall barrier material upon sidewalls of the interconnect metallization line and over the dielectric material.

Assignees

• Intel Corp

Inventors

• Lin Kevin
• Sato Noriyuki
• Tronic Tristan
• Christenson Michael
• Jezewski Christopher
• Chen Jiun-Ruey
• Blackwell James M
• Metz Matthew
• Reshotko Miriam
• Kabir Nafees
• Bielefeld Jeffery
• Chandhok Manish
• Yoo Hui Jae
• Karpov Elijah
• Naylor Carl
• Chebiam Ramanan

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title