Self-aligned interconnect features with floating dielectric structure

Patent metadata

Field	Value
Publication number	US-2025218868-A1
Application number	US-202318397247-A
Country	US
Kind code	A1
Filing date	Dec 27, 2023
Priority date	Dec 27, 2023
Publication date	Jul 3, 2025
Grant date	—

Abstract

An integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. The integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. An opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. The second interconnect feature extends through the opening. In an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). In an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a first interconnect feature extending within a first dielectric material; a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature; and a layer having (i) a first section and (ii) a second section that is discontinuous with the first section, the layer comprising a second dielectric material that is compositionally different from the first dielectric material; wherein an opening between the first section and the second section is above the first interconnect feature; wherein the second interconnect feature extends through the opening; and wherein a lower surface of each of the first section and the second section is vertically separated from an upper surface of the first interconnect feature by at least 2 nanometers (nm).

2 . The integrated circuit device of claim 1 , wherein at least a part of an upper surface and at least a part of the lower surface of each of the first and second sections is in contact with the first dielectric material.

3 . The integrated circuit device of claim 1 , wherein no portion of the first dielectric material is between at least a portion of the second interconnect feature and the first section, and no portion of the first dielectric material is between at least another portion of the second interconnect feature and the second section.

4 . The integrated circuit device of claim 1 , further comprising:
a third interconnect feature extending within the first dielectric material, and laterally adjacent to and separated from the first interconnect feature by the first dielectric material, with no other interconnect feature landing on the third interconnect feature; wherein the layer comprises a third section that is discontinuous with each of the first and second sections; wherein another opening between the second section and the third section is above, and vertically aligned to, the third interconnect feature; and where each of the lower surface of the second section and a lower surface of the third section is vertically separated from an upper surface of the third interconnect feature by at least 2 nm.

5 . The integrated circuit device of claim 4 , wherein the third section comprising the second dielectric material is fully surrounded on all sides by the first dielectric material.

6 . The integrated circuit device of claim 1 , wherein the opening between the first section and the second section is vertically aligned to the first interconnect feature.

7 . The integrated circuit device of claim 1 , wherein each of the first interconnect feature and the second interconnect feature is one of a conductive via or a conductive line.

8 . The integrated circuit device of claim 1 , wherein the first dielectric material is a low-k dielectric material, and the second dielectric material is a high-k dielectric material.

9 . The integrated circuit device of claim 1 , wherein a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.

10 . The integrated circuit device of claim 1 , wherein the lower surface of each of the first section and the second section is vertically separated from the upper surface of the first interconnect feature by at least 4 nm.

11 . The integrated circuit device of claim 1 , wherein the lower surface of each of the first section and the second section is vertically separated from the upper surface of the first interconnect feature by a vertical distance in the range of 5 nm to 20 nm.

12 . The integrated circuit device of claim 1 , wherein a thickness of each of the first section and the second section is in the range of 5 angstroms to 50 angstroms, and wherein the thickness is measured in a vertical direction and along a height of the first and second interconnect features.

13 . The integrated circuit device of claim 1 , wherein an upper surface of the second interconnect feature has a first width and a lower surface of the second interconnect feature has a second width, wherein the first and second widths are measured in a direction perpendicular to a direction of a height of the first and second interconnect features, and wherein the first width is least 1.2 times the second width.

14 . An integrated circuit device comprising:
a first interconnect feature and a laterally adjacent second interconnect feature, each of the first and second interconnect features extending through and separated by a first dielectric material; a layer comprising a first section, a second section, and a third section, wherein the layer comprises a second dielectric material having a dielectric constant different from a dielectric constant of the first dielectric material, and wherein each of the first, second, third sections are discontinuous from other and are on a horizontal plane that is (i) above the first and second interconnect features, and (ii) vertically separated from the first and second interconnect features by at least 2 nanometers; wherein a first opening between the first and second sections is above the first interconnect feature, and a second opening between the second and third sections is above the second interconnect feature; and wherein at least one of the first, second, and third sections are surrounded on all sides by the first dielectric material.

15 . The integrated circuit device of claim 14 , further comprising:
a third interconnect feature landing on the first interconnect feature, wherein the third interconnect feature is within 1 nm of each of the first section and the second section, wherein the third section is surrounded on all sides by the first dielectric material.

16 . The integrated circuit device of claim 15 , wherein the third interconnect feature is in contact with each of the first section and the second section.

17 . The integrated circuit device of claim 14 , wherein the dielectric constant of the second dielectric material is higher than the dielectric constant of the first dielectric material.

18 . A method comprising:
depositing a conductive material, and a masking material thereon; patterning the masking material, and removing at least portions of the conductive material not covered by the patterned masking material, to form a plurality of interconnect features comprising the conductive material; depositing a first dielectric material to at least in part surround the plurality of interconnect features and the patterned masking material, wherein upper surfaces of the patterned masking material are exposed through an upper surface of the first dielectric material; selectively depositing a second dielectric material on the upper surface of the first dielectric material, without depositing the second dielectric material on the upper surfaces of the patterned masking material, wherein the second dielectric material forms a plurality of sections of a layer; and removing the patterned masking material.

19 . The method of claim 18 , further comprising:
further depositing the first dielectric material on the plurality of sections of the layer of the second dielectric material,
wherein the plurality of sections includes a first section, a second section, and a third section,
wherein a first opening between the first and second sections is above a first interconnect feature of the plurality of interconnect features, and a second opening between the second and third sections is above a second interconnect feature of

Assignees

• Intel Corp

Inventors

• Naskar Sudipto
• Jezewski Christopher J
• Peer Akshit
• Dutta Ananya
• Chen Jiun-Ruey
• Metz Matthew V
• Kobrinsky Mauro J
• Walker Bryce C
• Esan Dominic
• Han Weimin C

Classifications

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title