Hybrid isolation capacitors in series
US-12490443-B2 · Dec 2, 2025 · US
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Bonifield Thomas D patents
Bonifield Thomas D is listed as an inventor on 43 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Bonifield Thomas D |
| Total patents | 43 |
| First publication | Mar 5, 2015 |
| Latest publication | Dec 2, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Device isolator with reduced parasitic capacitance
US-11869933-B2 · Jan 9, 2024 · US
Integrated capacitor with sidewall having reduced roughness
US-11798979-B2 · Oct 24, 2023 · US
Hybrid isolation capacitors in series
US-2023129461-A1 · Apr 27, 2023 · US
Hybrid high and low stress oxide embedded capacitor dielectric
US-11495658-B2 · Nov 8, 2022 · US
Method of fabricating a thick oxide feature on a semiconductor wafer
US-11205695-B2 · Dec 21, 2021 · US
Device isolator with reduced parasitic capacitance
US-2021367030-A1 · Nov 25, 2021 · US
Device isolator with reduced parasitic capacitance
US-11107883-B2 · Aug 31, 2021 · US
Generating multi-focal defect maps using optical tools
US-11087451-B2 · Aug 10, 2021 · US
Scribe seals and methods of making
US-11069627-B2 · Jul 20, 2021 · US
Recent patents
Latest publications not already listed above.
Integrated capacitor with sidewall having reduced roughness
US-2021143249-A1 · May 13, 2021 · US
Integrated capacitor with sidewall having reduced roughness
US-10978548-B2 · Apr 13, 2021 · US
Hydrogen ventilation of CMOS wafers
US-10886120-B2 · Jan 5, 2021 · US
Methods and apparatus for high voltage integrated circuit capacitors
US-10847605-B2 · Nov 24, 2020 · US
High voltage galvanic isolation device
US-10707297-B2 · Jul 7, 2020 · US
Hydrogen ventilation of cmos wafers
US-2020058485-A1 · Feb 20, 2020 · US
Hybrid High and Low Stress Oxide Embedded Capacitor Dielectric
US-2019378892-A1 · Dec 12, 2019 · US
Method of fabricating a thick oxide feature on a semiconductor wafer
US-2019198604-A1 · Jun 27, 2019 · US
Generating multi-focal defect maps using optical tools
US-2019188839-A1 · Jun 20, 2019 · US
Device isolator with reduced parasitic capacitance
US-2019148486-A1 · May 16, 2019 · US
High voltage galvanic isolation device
US-2019074350-A1 · Mar 7, 2019 · US
Device isolator with reduced parasitic capacitance
US-10186576-B2 · Jan 22, 2019 · US
High voltage galvanic isolation device
US-10147784-B2 · Dec 4, 2018 · US
Crack deflector structure for improving semiconductor device robustness against saw-induced damage
US-10109597-B2 · Oct 23, 2018 · US
Integrated capacitor with sidewall having reduced roughness
US-2018130870-A1 · May 10, 2018 · US
Device isolator with reduced parasitic capacitance
US-2018026095-A1 · Jan 25, 2018 · US
Device isolator with reduced parasitic capacitance
US-9806148-B2 · Oct 31, 2017 · US
Methods and apparatus for high voltage integrated circuit capacitors
US-2017309702-A1 · Oct 26, 2017 · US
High breakdown voltage microelectronic device isolation structure with improved reliability
US-9768245-B2 · Sep 19, 2017 · US
High voltage galvanic isolation device
US-2017263696-A1 · Sep 14, 2017 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Texas Instruments Inc | 43 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D1/68 | 32 |
| H10W20/496 | 30 |
| H10D1/692 | 28 |
| H10W72/536 | 27 |
| H01L28/40 | 24 |