Device isolator with reduced parasitic capacitance

Patent metadata

Field	Value
Publication number	US-9806148-B2
Application number	US-201514680211-A
Country	US
Kind code	B2
Filing date	Apr 7, 2015
Priority date	Apr 7, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.

First claim

What is claimed is:

1. An isolator structure in an integrated circuit, comprising:
a first buried doped layer of a first conductivity type disposed within a substrate of a second conductivity type, the first buried doped layer located beneath a surface of the substrate;
a first tank region of the second conductivity type overlying a portion of the first buried doped layer;
a first well region of the first conductivity type disposed at the surface of the substrate and overlying a portion of the first tank region;
a first boundary doped region of the first conductivity type disposed at the surface of the substrate and laterally surrounding the first tank region, the first boundary doped region extending into the surface of the substrate and contacting the first buried doped layer;
a first conductor element disposed near the surface of the substrate at a location overlying the first well region, separated therefrom by dielectric material; and
a second conductor element disposed near the surface of the substrate at a location overlying the first conductor element, separated therefrom by dielectric material.

2. The structure of claim 1 , wherein the first and second conductor elements each comprise a capacitor plate.

3. The structure of claim 1 , wherein the first and second conductor elements each comprise an inductor coil.

4. The structure of claim 1 , wherein an external terminal of the integrated circuit is electrically connected to the second conductor element.

5. The structure of claim 1 , further comprising:
a first doped region of the second conductivity type formed at a location of the surface of the substrate within the first tank region;
a second doped region of the second conductivity type formed at a location of the surface of the substrate outside of the first boundary doped region relative to the first well region;
a third conductor element in electrical contact with the first doped region, for applying a bias voltage to the tank region; and
a fourth conductor element in electrical contact with the second doped region, for applying a bias voltage to the substrate.

6. The structure of claim 5 , further comprising:
a fifth conductor element, in electrical contact with the first well region for applying a bias voltage to the first well region; and
a sixth conductor element, in electrical contact with the first boundary doped region, for applying a bias voltage to the first boundary doped region.

7. The structure of claim 6 , further comprising:
a plurality of resistors formed into the integrated circuit, each coupled in series with one of the third, fourth, fifth, and sixth conductor elements.

8. The structure of claim 7 , wherein the first conductivity type is n-type and the second conductivity type is p-type;
and wherein the bias voltage applied by the fifth and sixth conductor elements to the first well region and the first boundary doped region via corresponding resistors is higher than the bias voltage applied by the third and fourth conductor elements to the first tank region and the substrate via corresponding resistors.

9. The structure of claim 6 , wherein the first conductivity type is n-type and the second conductivity type is p-type;
and wherein the bias voltage applied by the fifth and sixth conductor elements to the first well region and the first boundary doped region is higher than the bias voltage applied by the third and fourth conductor elements to the first tank region and the substrate.

10. The structure of claim 1 , wherein the first boundary doped region comprises:
a first buried isolation doped region, formed into the substrate at a depth beneath the surface of the substrate and contacting the first buried doped layer; and
a second well region disposed at the surface of the substrate, and overlying and contacting the first buried isolation doped region.

11. The structure of claim 1 , further comprising:
a second tank region of the second conductivity type underlying the first buried doped layer and surrounding the first boundary doped region;
a second buried doped layer of the first conductivity type underlying the second tank region; and
a second boundary doped region of the first conductivity type disposed at the surface of the substrate and laterally surrounding the second tank region, the second boundary doped region extending into the surface of the substrate and contacting the second buried doped layer.

12. An electronic system, comprising:
a first integrated circuit having an external terminal;
a second integrated circuit having an external terminal, the second integrated circuit including an isolator structure comprising:
a buried doped layer of a first conductivity type disposed within a substrate of a second conductivity type, the buried doped layer located beneath a surface of the substrate;
a tank region of the second conductivity type overlying a portion of the buried doped layer;
a first well region of the first conductivity type disposed at the surface of the substrate and overlying a portion of the tank region;
a boundary doped region of the first conductivity type disposed at the surface of the substrate and laterally surrounding the tank region, the boundary doped region extending into the surface of the substrate and contacting the buried doped layer;
a first conductor element disposed near the surface of the substrate at a location overlying the first well region, separated therefrom by dielectric material; and
a second conductor element disposed near the surface of the substrate at a location overlying the first conductor element, separated therefrom by dielectric material, and in electrical contact with the external terminal of the second integrated circuit; and
a connector connecting the external terminal of the first integrated circuit to the external terminal of the second integrated circuit.

13. The system of claim 12 , wherein the isolator structure forms a capacitor.

14. The system of claim 12 , wherein the isolator structure forms an inductive transformer.

15. The system of claim 12 , wherein the boundary doped region comprises:
a buried isolation region, formed into the substrate at a depth beneath the surface of the substrate and contacting the buried doped layer; and
a second well region disposed at the surface of the substrate, and overlying and contacting the buried isolation region.

16. The system of claim 12 , wherein the second integrated circuit further comprises:
bias circuitry for applying a reverse bias voltage to the boundary doped region relative to the tank region and the substrate.

Assignees

• Texas Instruments Inc

Inventors

• Selvaraj Raja
• Kamath Anant Shankar
• Williams Byron Lovell
• Bonifield Thomas D
• Arch John Kenneth

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title