Method of fabricating a thick oxide feature on a semiconductor wafer

Patent metadata

Field	Value
Publication number	US-11205695-B2
Application number	US-201715850999-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Dec 21, 2017
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit comprising:
forming an oxide layer between an etch stop layer and an upper metal plate, the oxide layer having a thickness of at least six micrometers, the oxide layer having a first etch rate of X with a given etchant;
depositing a photoresist layer over the oxide layer, the photoresist layer having a second etch rate of Y with the given etchant, wherein the ratio of X:Y is less than 4:1;
prior to etching the photoresist layer and the oxide layer, patterning the photoresist layer with a grayscale mask, thereby creating a sloped photoresist layer having a sidewall that forms an angle with respect to the substrate surface that is less than or equal to 10 degrees; and
etching the photoresist layer and the oxide layer using a plurality of timed etch segments, each etch segment removing a portion of the oxide layer and being separated from a subsequent etch segment by a pause during which the etch process is halted.

2. The method as recited in claim 1 wherein the ratio of X:Y is less than 3:1.

3. The method as recited in claim 1 further comprising forming an etch stop layer underneath the oxide layer.

4. The method as recited in claim 3 further comprising performing a final etch segment that stops on the etch stop layer.

5. The method as recited in claim 4 wherein the oxide layer comprises a material chosen from the group comprising silicon oxide, aluminum oxide, tantalum oxide and hafnium oxide.

6. A method of fabricating an integrated circuit, comprising:
forming an oxide layer over an etch stop layer;
depositing and patterning a photoresist layer over the oxide layer;
performing a plurality of etch segments, each etch segment etching the photoresist layer and the oxide layer using a same etch process, each segment followed by a pause during which the etch process is halted and byproducts of the etch process are evacuated, the etch process etching the oxide layer before and after each pause; and
performing a final etch segment of the photoresist layer and the oxide layer that stops on the etch stop layer.

7. The method as recited in claim 6 wherein the etch process utilizes a plasma etch process.

8. The method as recited in claim 6 wherein the etch process re-optimizes the plasma etch process after each pause.

9. The method as recited in claim 6 wherein the pauses last between 15 and 60 seconds.

10. The method as recited in claim 6 further comprising, prior to etching the photoresist layer and the oxide layer, patterning the photoresist layer with a grayscale mask.

11. The method as recited in claim 10 wherein the oxide layer has a first etch rate of X, the photoresist layer has a second etch rate of Y, and the ratio of X:Y is less than 4:1.

12. The method as recited in claim 6 wherein the etch stop layer comprises silicon oxynitride.

13. The method as recited in claim 6 wherein the oxide layer comprises a material chosen from the group comprising silicon oxide, aluminum oxide, tantalum oxide and hafnium oxide.

14. A method of fabricating an integrated capacitor, the method comprising:
forming a silicon oxide layer having a thickness of at least six micrometers, the silicon oxide layer having a first etch rate of X with a given etchant;
depositing a photoresist layer directly on the silicon oxide layer, the photoresist layer having a second etch rate of Y with the given etchant, wherein the ratio of X:Y is less than 4:1;
prior to etching the photoresist layer and the silicon oxide layer using the etchant, patterning the photoresist layer with a grayscale mask; and
etching the photoresist layer and the silicon oxide layer using a plasma etching process to form a sloped silicon oxide feature, wherein the etching is performed in a plurality of etch segments that are separated by pauses during which the plasma etching process is halted and the byproducts of the plasma etching process are evacuated, each of the etch segments etching the silicon oxide layer.

Assignees

• Texas Instruments Inc

Inventors

• Stewart Elizabeth C
• West Jeffrey Alan
• Bonifield Thomas D
• Chun Jay Sung
• Williams Byron Lovell

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title