Hybrid high and low stress oxide embedded capacitor dielectric

Patent metadata

Field	Value
Publication number	US-11495658-B2
Application number	US-201916435095-A
Country	US
Kind code	B2
Filing date	Jun 7, 2019
Priority date	Jun 8, 2018
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a metal top plate located over a substrate;
a metal bottom plate located between the top plate and the substrate;
a high-stress compressive silicon dioxide layer located between the bottom plate and the substrate; and
at least one low-stress compressive silicon dioxide layer located between the top plate and the bottom plate.

2. The integrated circuit of claim 1 , wherein the high-stress silicon dioxide layer and the low-stress silicon dioxide layer are formed using a PE-TEOS process.

3. The integrated circuit of claim 1 , further comprising a metal guard ring surrounding the top plate and the bottom plate.

4. The integrated circuit of claim 3 , further comprising a transistor formed over the substrate, the guard ring located between the transistor and the bottom plate.

5. The integrated circuit of claim 1 , wherein the at least one low-stress silicon dioxide layer includes a first PE-TEOS layer, and further comprising an HDP oxide layer between and touching the first PE-TEOS layer and a second PE-TEOS layer.

6. The integrated circuit of claim 5 , wherein a first IMD level includes the first PE-TEOS layer and the HDP oxide layer, and the at least one low-stress silicon dioxide layer includes a third PE-TEOS layer, and further comprising a second IMD level including the third PE-TEOS layer and a second HDP oxide layer, the second IMD level located between the first IMD level and the top plate.

7. The integrated circuit of claim 1 , wherein the at least one low-stress compressive silicon dioxide layer is one of a plurality of low-stress silicon dioxide layers located between the high-stress silicon dioxide layer and the top plate, each of the low-stress silicon dioxide layers touching a neighboring low-stress silicon dioxide layer.

8. The integrated circuit of claim 1 , wherein the low-stress compressive silicon dioxide layer has a compressive stress in a range from about 15 MPa to about 40 MPa and the high-stress compressive dielectric layer has a compressive stress in a range from about 80 MPa to about 160 MPa.

9. The integrated circuit of claim 1 , further comprising an HDP oxide layer touching sidewalls and a top surface of the top plate.

10. The integrated circuit of claim 1 , wherein the top plate is located directly on a silicon nitride layer.

11. The integrated circuit of claim 1 , wherein the top plate touches the high-stress compressive silicon oxide layer.

12. The integrated circuit of claim 1 , wherein the top plate and the bottom plate are both circular with a diameter of about 100 μm.

13. The integrated circuit of claim 1 , wherein the top plate and the bottom plate each have a long axis with a length of about 160 μm and a short axis with a length of about 120 μm.

14. A method of forming an integrated circuit, comprising:
forming a metal top plate over a substrate;
forming a metal bottom plate between the top plate and the substrate;
forming a high-stress compressive silicon dioxide layer between the bottom plate and the substrate; and
forming at least one low-stress compressive silicon dioxide layer between the top plate and the bottom plate.

15. The method of claim 14 , wherein the high-stress silicon dioxide layer and the low-stress silicon dioxide layer are formed using a PE-TEOS process.

16. The method of claim 14 , wherein forming the low-stress silicon dioxide layer includes forming a PE-TEOS layer in a capacitively coupled reactor using about 600 W power, about 667 Pa pressure, about 1700 mgm TEOS feed rate; and forming said high-stress silicon dioxide layer includes forming a PE-TEOS layer in a capacitively coupled reactor using about 850 W power, about 1093 Pa pressure, about 1900 mgm TEOS feed rate.

17. The method of claim 14 , further comprising forming a guard ring surrounding the top plate and the bottom plate.

18. The method of claim 17 , further comprising forming a transistor over the substrate, the guard ring located between the transistor and the bottom plate.

19. The method of claim 14 , wherein the at least one low-stress silicon dioxide layer is a first PE-TEOS layer, and further comprising forming an HDP oxide layer between and touching the first PE-TEOS layer and a second PE-TEOS layer.

20. The method of claim 19 , wherein a first IMD level includes the first PE-TEOS layer and the HDP oxide layer, and the at least one low-stress silicon dioxide layer includes a third PE-TEOS layer, and further comprising forming a second IMD level including the third PE-TEOS layer and a second HDP oxide layer, the second IMD level located between the first IMS level and the top plate.

21. The method of claim 14 , wherein the at least one low-stress silicon dioxide layer is one of a plurality of low-stress silicon dioxide layers located between the high-stress silicon dioxide layer and the top plate, each of the low-stress silicon dioxide layers touching a neighboring low-stress silicon dioxide layer.

22. The method of claim 14 , wherein the at least one low-stress compressive dielectric layer has a compressive stress in a range from about 15 MPa to about 40 MPa and the high-stress compressive dielectric layer has a compressive stress in a range from about 80 MPa to about 160 MPa.

23. The method of claim 14 , further comprising forming an HDP oxide layer that touches sidewalls and a top surface of the top plate.

24. The method of claim 14 , further comprising forming a silicon nitride layer between the top plate and the low-stress silicon dioxide layer, wherein the top plate touches the silicon nitride layer.

25. An integrated circuit, comprising:
a semiconductor substrate having top and bottom metal plates formed thereover, the bottom plate located between the top plate and the substrate;
a first compressive HDP oxide layer formed over and touching the bottom metal plate;
a first compressive low-stress silicon dioxide layer located over and touching the first HDP oxide layer;
a first compressive high-stress silicon dioxide layer located over and touching the first low-stress silicon dioxide layer;
a second compressive HDP oxide layer formed over and touching the first high-stress silicon dioxide layer;
a second compressive low-stress silicon dioxide layer located over and touching the second HDP oxide layer; and
a second compressive high-stress silicon dioxide layer located over and touching the second low-stress silicon dioxide layer.

Assignees

• Texas Instruments Inc

Inventors

• Stewart Elizabeth Costner
• West Jeffrey A
• Bonifield Thomas D

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L27/0733

  Electricity · mapped topic